COMBINED SPARSE AND BLOCK FLOATING ARITHMETIC
Granted: June 20, 2024
Application Number:
20240201948
A processing device for encoding floating point numbers comprising memory configured to store data comprising the floating point numbers and circuitry. The circuitry is configured to, for a set of the floating point numbers, identify which of the floating point numbers represent a zero value and which of the floating point numbers represent a non-zero value, convert the floating point numbers which represent a non-zero value into a block floating point format value and generate an…
METHOD AND APPARATUS FOR MANAGING MEMORY
Granted: June 20, 2024
Application Number:
20240201876
A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual…
DYNAMIC CONFIGURATION OF PROCESSOR SUB-COMPONENTS
Granted: June 20, 2024
Application Number:
20240201777
The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.
Accessing a Cache Based on an Address Translation Buffer Result
Granted: June 13, 2024
Application Number:
20240193097
Address translation is performed to translate a virtual address targeted by a memory request (e.g., a load or memory request for data or an instruction) to a physical address. This translation is performed using an address translation buffer, e.g., a translation lookaside buffer (TLB). One or more actions are taken to reduce data access latencies for memory requests in the event of a TLB miss where the virtual address to physical address translation is not in the TLB. Examples of actions…
FEED FORWARD TRAINING OF MEMORY INTERFACES
Granted: June 13, 2024
Application Number:
20240192858
A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA…
TECHNIQUE FOR IMPROVING POWER STATE TRANSITION LATENCY FOR COMPUTING DEVICE
Granted: June 13, 2024
Application Number:
20240192760
A disclosed technique includes in response to a trigger to power a functional element of a device to a lower power state, operating a set of backup state elements for the functional element in a lower power mode; and resuming operation of the functional element and the backup state elements in a higher power state.
VERTEX INDEX ROUTING THROUGH CULLING SHADER FOR TWO LEVEL PRIMITIVE BATCH BINNING
Granted: May 23, 2024
Application Number:
20240169641
Techniques for performing rendering operations are disclosed herein. The techniques include providing indices and vertices to a culling shader; culling primitives and outputting primitives and indices that are not culled; and generating information for a fine binning pass based on the indices and primitives that are not culled.
EFFICIENT REDUCE-SCATTER VIA NEAR-MEMORY COMPUTATION
Granted: May 23, 2024
Application Number:
20240168639
An apparatus for performing distributed reduction operations using near-memory computation includes memory and a first near-memory compute node. The first-near-memory compute node is coupled to a plurality of near-memory compute nodes. The first near-memory compute node comprises logic to store first data loaded from a second near-memory compute node, perform a reduction operation on the first data and second data to compute a result; and store the result within the first near-memory…
LOW POWER AND HIGH SPEED SCAN DUMP
Granted: May 23, 2024
Application Number:
20240168513
A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.
METHOD AND APPARATUS FOR NORMALIZING AN IMAGE IN AN IMAGE CAPTURING DEVICE
Granted: May 16, 2024
Application Number:
20240163564
A method and apparatus for normalizing an image in an image capturing device includes receiving a processed image by the image device. The processed image is brightness normalized to create a brightness normalized image. The brightness normalized image is provided to an artificial intelligence engine for processing.
SYSTEMS AND METHODS FOR DISABLING FAULTY CORES USING PROXY VIRTUAL MACHINES
Granted: May 9, 2024
Application Number:
20240152434
A device for disabling faulty cores using proxy virtual machines includes a processor, a faulty core, and a physical memory. The processor is responsible for executing a hypervisor that is configured to assign a proxy virtual machine to the faulty core. The assigned proxy virtual machine also includes a minimal workload. Various other methods, systems, and computer-readable media are also disclosed.
APPARATUSES AND SYSTEMS FOR OFFSET CROSS FIELD-EFFECT TRANSISTORS
Granted: May 2, 2024
Application Number:
20240145565
The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer. The second transistor can include a second channel that is oriented in a direction orthogonal to the first direction, and the first channel and the second channel can be laterally offset such that the second channel does not…
VARIABLE BIT MORTON CODES
Granted: May 2, 2024
Application Number:
20240144581
A technique for performing ray tracing operations is provided. The technique includes determining a set of keys and a set of values corresponding to dimensions of a bounding box for a scene; sorting the set of keys and the set of values to generate a sorted set of values; and based on the sorted set of values, generating a Morton code for a triangle of the scene.
SPLIT-BASED TREES FOR RAY TRACING
Granted: May 2, 2024
Application Number:
20240144580
Devices and methods are provided for generating an accelerated data structure for ray tracing which include generating a first splitting plane at a first location of a space comprising objects represented by geometry, constructing a first level of an accelerated data structure based on portions of the geometry, straddling the first splitting plane, which are classified as located on opposing sides of the first splitting plane, after constructing the first level of the accelerated data…
Stability Testing for Memory Overclocking
Granted: May 2, 2024
Application Number:
20240143445
Stability testing for memory overclocking is described. In accordance with the described techniques, operation of a memory with overclocked memory settings is testing during a boot up process of a computing device. Test results based on the testing are exposed via a user interface. The test results predict a stability of the memory over a subsequent time period if the memory is configured to operate with the overclocked memory settings.
SOFTWARE COMPILATION FOR NETWORKED PROCESSING SYSTEM
Granted: May 2, 2024
Application Number:
20240143295
A compilation technique is provided. The technique includes including a first instruction into a first executable for a first auxiliary processor, wherein the first instruction specifies execution by the first auxiliary processor; and including a second instruction into the first executable, wherein the second instruction targets resources that have affinity with the first auxiliary processor.
Sparse Matrix Operations Using Processing-in-Memory
Granted: May 2, 2024
Application Number:
20240143199
Sparse matrix operations using processing-in-memory is described. In accordance with the described techniques, a processing-in-memory component of a memory module receives a request for a vector element stored at a first location in memory of the memory module. The processing-in-memory component identifies an index value for a non-zero element in a sparse matrix using a representation of the sparse matrix stored at a second location in the memory. The processing-in-memory component then…
HYBRID RENDER WITH DEFERRED PRIMITIVE BATCH BINNING
Granted: April 25, 2024
Application Number:
20240135626
A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin…
Data Routing for Efficient Decompression of Compressed Data Stored in a Cache
Granted: April 25, 2024
Application Number:
20240134793
Data routing for efficient decompressor use is described. In accordance with the described techniques, a cache controller receives requests from multiple requestors for elements of data stored in a compressed format in a cache. The requests include at least a first request from a first requestor and a second request from a second requestor. A decompression routing system identifies a redundant element of data requested by both the first requestor and the second requestor and causes…
READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES
Granted: April 11, 2024
Application Number:
20240119993
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only…
