Adaptive biasing circuit for serial communication interfaces
Granted: September 19, 2023
Patent Number:
11764789
Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a…
Using sub-networks created from neural networks for processing color images
Granted: September 19, 2023
Patent Number:
11763155
A system comprising an electronic device that includes a processor is described. During operation, the processor acquires a full version of a neural network, the neural network including internal elements for processing instances of input image data having a set of color channels. The processor then generates, from the neural network, a set of sub-networks, each sub-network being a separate copy of the neural network with the internal elements for processing at least one of the color…
Cuckoo filters and cuckoo hash tables with biasing, compression, and decoupled logical sparsity
Granted: September 19, 2023
Patent Number:
11762828
A method includes, for each key of a plurality of keys, identifying from a set of buckets a first bucket for the key based on a first hash function, and identifying from the set of buckets a second bucket for the key based on a second hash function. An entry for the key is stored in a bucket selected from one of the first bucket and the second bucket. The entry is inserted in a sequence of entries in a memory block. A position of the entry in the sequence of entries corresponds to the…
Method and apparatus for a dram cache tag prefetcher
Granted: September 19, 2023
Patent Number:
11762777
Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a…
Matrix multiplication unit with flexible precision operations
Granted: September 19, 2023
Patent Number:
11762658
A processing unit such as a graphics processing unit (GPU) includes a plurality of vector signal processors (VSPs) that include multiply/accumulate elements. The processing unit also includes a plurality of registers associated with the plurality of VSPs. First portions of first and second matrices are fetched into the plurality of registers prior to a first round that includes a plurality of iterations. The multiply/accumulate elements perform matrix multiplication and accumulation on…
Performing scan data transfer inside multi-die package with SERDES functionality
Granted: September 19, 2023
Patent Number:
11762017
A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A…
Dynamic repartition of memory physical address mapping
Granted: June 27, 2023
Patent Number:
11687251
Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices…
Network cache injection for coherent GPUs
Granted: June 27, 2023
Patent Number:
11687460
Methods, devices, and systems for GPU cache injection. A GPU compute node includes a network interface controller (NIC) which includes NIC receiver circuitry which can receive data for processing on the GPU, NIC transmitter circuitry which can send the data to a main memory of the GPU compute node and which can send coherence information to a coherence directory of the GPU compute node based on the data. The GPU compute node also includes a GPU which includes GPU receiver circuitry which…
Memory coloring for executing operations in concurrent paths of a graph representing a model
Granted: June 27, 2023
Patent Number:
11687456
An electronic device that handles memory accesses includes a memory and a processor that supports a plurality of streams. The processor acquires a graph that includes paths of operations in a set of operations for processing instances of data through a model, each path of operations including a separate sequence of operations from the set of operations that is to be executed using a respective stream from among the plurality of streams. The processor then identifies concurrent paths in…
DRAM command streak efficiency management
Granted: June 27, 2023
Patent Number:
11687281
A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a…
Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training
Granted: June 20, 2023
Patent Number:
11682445
A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.
Using error correction code (ECC) bits for retaining victim cache lines in a cache block in a cache memory
Granted: June 20, 2023
Patent Number:
11681620
An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in…
Dynamic multi-bank memory command coalescing
Granted: June 20, 2023
Patent Number:
11681465
Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the…
Predicting processor power disturbances by monitoring performance characteristics
Granted: June 13, 2023
Patent Number:
11675410
A monitoring system predicts voltage droops at a processor by monitoring one or more performance characteristics of the processor, selecting a response policy based on the prediction, and adjusting a parameter of the processor. Multiple predictions of voltage droop conditions at different locations of the processor are made simultaneously, with the processor generating one or more responses and resulting in adjusting one or more parameters of the processor. By predicting voltage droop…
Memory with expandable row width
Granted: June 13, 2023
Patent Number:
11676659
A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a…
Graphics library extensions
Granted: June 13, 2023
Patent Number:
11676321
A method and system for performing graphics processing is provided. The method and system includes storing stencil buffer values in a stencil buffer; generating either or both of a reference value and a source value in a fragment shader; comparing the stencil buffer values against the reference value; and processing a fragment based on the comparing the stencil buffer values against the reference value.
Enhanced low-priority arbitration
Granted: June 13, 2023
Patent Number:
11675718
A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.
Memory request throttling to constrain memory bandwidth utilization
Granted: June 13, 2023
Patent Number:
11675703
A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an…
DDR memory error recovery
Granted: June 13, 2023
Patent Number:
11675659
In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a…
Dual vector arithmetic logic unit
Granted: June 13, 2023
Patent Number:
11675568
A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a…
