Error pin training with graphics DDR memory
Granted: November 26, 2024
Patent Number:
12154656
A receiver is trained for receiving a signal over a data bus. A volatile memory is commanded over the data bus to place a selected pulse-amplitude modulation (PAM) driver in a mode with a designated steady output level. At a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the designated steady output level is swept through a range of voltages and the respective reference voltage is compared to a voltage received from the PAM driver to…
Droop mitigation for an inter-chiplet interface
Granted: November 19, 2024
Patent Number:
12147366
Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the…
Leveraging processing in memory registers as victim buffers
Granted: November 19, 2024
Patent Number:
12147338
In accordance with the described techniques for leveraging processing in memory registers as victim buffers, a computing device includes a memory, a processing in memory component having registers for data storage, and a memory controller having a victim address table that includes at least one address of a row of the memory that is stored in the registers. The memory controller receives a request to access the row of the memory and accesses data of the row from the registers based on…
Load instruction for multi sample anti-aliasing
Granted: November 12, 2024
Patent Number:
12141915
Techniques for performing multi-sample anti-aliasing operations are provided. The techniques include detecting an instruction for a multi-sample anti-aliasing load operation; determining a sampling rate of source data for the load operation, data storage format of the source data, and loading mode indicating whether the load operation requests same or different color components, or depth data; and based on the determined sampling rate, data storage format, and loading mode, load data…
Probe filter directory management
Granted: November 12, 2024
Patent Number:
12141066
A data processing system includes a plurality of coherent masters, a plurality of coherent slaves, and a coherent data fabric. The coherent data fabric has upstream ports coupled to the plurality of coherent masters and downstream ports coupled to the plurality of coherent slaves for selectively routing accesses therebetween. The coherent data fabric includes a probe filter and a directory cleaner. The probe filter is associated with at least one of the downstream ports and has a…
Error recovery for non-volatile memory modules
Granted: November 12, 2024
Patent Number:
12141038
A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the…
Data fabric C-state management
Granted: November 5, 2024
Patent Number:
12135601
A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the…
Forward rendering pipeline with light culling
Granted: November 5, 2024
Patent Number:
12136165
A method for enhanced forward rendering is disclosed which includes a depth pre-pass, light culling and a final shading. The depth pre-pass minimizes the cost of final shading by avoiding high pixel overdraw. The light culling stage calculates a list of light indices overlapping a pixel. The light indices are calculated on a per-tile basis, where the screen has been split into units of tiles. The final shading evaluates materials using information stored for each light. The forward…
Flexible dictionary sharing for compressed caches
Granted: November 5, 2024
Patent Number:
12135653
Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the…
Devices, systems, and methods for injecting fabricated errors into machine check architectures
Granted: November 5, 2024
Patent Number:
12135625
An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a…
Low power and high speed scan dump
Granted: November 5, 2024
Patent Number:
12135577
A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.
Technique for extended idle duration for display to improve power consumption
Granted: October 29, 2024
Patent Number:
12130690
A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
Apparatus, system, and method for calibrating high-speed communication interfaces to transmission lines
Granted: October 29, 2024
Patent Number:
12132460
A computing device for calibrating high-speed communication interfaces to transmission lines may include an impedance-matching driver with a plurality of independently controllable impedance stages that facilitate matching an impedance of a transmission line. The computing device may also include a controller communicatively coupled to the impedance-matching driver via a plurality of control signals grouped into a first group of control signals that control a first stage included in the…
Workgroup synchronization and processing
Granted: October 29, 2024
Patent Number:
12131199
A processing system monitors and synchronizes parallel execution of workgroups (WGs). One or more of the WGs perform (e.g., periodically or in response to a trigger such as an indication of oversubscription) a waiting atomic instruction. In response to a comparison between an atomic value produced as a result of the waiting atomic instruction and an expected value, WGs that fail to produce a correct atomic value are identified as being in a waiting state (e.g., waiting for a…
Hardware accelerated dynamic work creation on a graphics processing unit
Granted: October 29, 2024
Patent Number:
12131186
A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a…
Methods and apparatus for offloading tiered memories management
Granted: October 29, 2024
Patent Number:
12131063
Methods and apparatus offload tiered memories management. The method includes obtaining a pointer to a stored memory management structure associated with tiered memories, where the memory management structure includes a plurality of memory management entries and each memory management entry of the plurality of memory management entries includes information for a memory section in one of the tiered memories. In some instances, the method includes scanning at least a part of the plurality…
Resource-aware compression
Granted: October 29, 2024
Patent Number:
12130741
Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression…
Autonomous organization and role selection of homogenous workers
Granted: October 29, 2024
Patent Number:
12130713
A method for configuring replicas in a distributed computing system is disclosed. In one example embodiment, a plurality of replicas with associated bootstrap modules may be created. The same bootstrap module code may be used for each replica, thereby simplifying configuration. Using the bootstrap module, the replicas may automatically configure themselves and self-assign a role for a set of predetermined roles such as master and worker. The bootstrap module may check a predetermined…
Residue-code-based error detection for cipher generation
Granted: October 29, 2024
Patent Number:
12130701
A processing unit employs a residue code (RC) to perform error detection and correction for a multi-round transformation data encryption process. The processing unit generates a cipher based on a plurality of transformations. For each of the plurality of transformations, the processing unit generates a corresponding residue code of a plurality of residue codes. The processing unit performs error detection for the cipher based on the plurality of residue codes.
Low power state selection based on idle duration history
Granted: October 29, 2024
Patent Number:
12130692
An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of…
