Logic for Synchronizing Multiple Tasks at Multiple Locations in an Instruction Stream
Granted: December 25, 2008
Application Number:
20080320485
Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to…
Macro to instantiate a variable used with a first macro requiring use of a second macro suitable for said variable
Granted: July 31, 2008
Application Number:
20080184197
A programmer creates a computer program in assembly language by use of a first macro to identify an operation to be performed on a variable without knowledge of one or more assembly language instructions required to perform the operation. A macro expander (that may be tightly coupled to an assembler) receives the programmer-specified first macro and its argument(s), uses the variable's class type to identify a macro name of a second macro, and invokes this second macro with the…
Flexible interconnect cable for an electronic assembly
Granted: May 22, 2008
Application Number:
20080116988
A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The cable can be coupled to electronic components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector…
Method of Accelerating the Shortest Path Problem
Granted: August 2, 2007
Application Number:
20070177512
The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into…
Use of different color sequences for variables of different sizes and different semantics
Granted: March 29, 2007
Application Number:
20070074190
Colors to be used in register allocation are grouped into a number of sequences. Each sequence is associated with an attribute (e.g. size and/or type) of variables whose nodes in an interference graph can be colored by colors in the sequence. In certain embodiments, in addition to the above-described grouping, colors within a group are ordered in a sequence. The specific order that is used may depend on, for example, an attribute (such as size) and a predetermined preference. One example…
Flexible interconnect cable with coplanar waveguide
Granted: February 22, 2007
Application Number:
20070040626
A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure. The cable can be coupled to destination components using a variety of connection techniques. The cable can also be…
System to provide fractional bandwidth data communications services
Granted: September 11, 2003
Application Number:
20030169756
A system to provide fractional bandwidth data transmission includes a network processor, physical layer device, or link layer device {“data device”) and a plurality of link layer devices that are coupled to a plurality of input-output ports. The link layer devices are coupled in a serial daisy chain fashion and pass data via a plurality of data channels. The first linked layer device is coupled to the data device and receives data therefrom and the last linked layer…
DS-3 desynchronizer
Granted: October 3, 2002
Application Number:
20020144169
A desynchronizer for smoothing gapped data signal and a gap clock signal extracted from a synchronous message is disclosed. A gap regulator module first re-maps the gapped data signal into a B-frame format and distributes the gaps in the data uniformly throughout the gapped data signal. A pointer leak logic module determines the bit leak rate as a function of received increment and decrement pointer adjustment signals. The pointer leak logic module determines the bit leak rate using…
