Applied Micro Circuits Patent Grants

Address index recovery using hash-based exclusive or

Granted: June 14, 2016
Patent Number: 9367454
Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Discrete time compensation mechanisms

Granted: May 17, 2016
Patent Number: 9344209
Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous…

Defect propagation of multiple signals of various rates when mapped into a combined signal

Granted: May 10, 2016
Patent Number: 9337959
Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective…

Scheduling memory banks based on memory access patterns

Granted: May 10, 2016
Patent Number: 9336164
Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory…

System and method for pre-fetching data based on a FIFO queue of packet messages reaching a first capacity threshold

Granted: May 10, 2016
Patent Number: 9336162
A method is provided for pre-fetching packet data prior to processing. The method accepts a plurality of packets and writes each packet into a memory. A message is derived for each packet, where each message includes a packet descriptor with a pointer to an address of the packet in the memory. Each message is added to a tail of a first-in first-out (FIFO) queue. A pre-fetch module examines a first message, if the first message reaches a first capacity threshold of the FIFO queue. If the…

Programmable gain amplifier with controlled gain steps

Granted: April 26, 2016
Patent Number: 9325287
Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the…

Large receive offload functionality for a system on chip

Granted: March 29, 2016
Patent Number: 9300578
Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network…

Frequency synthesis with gapper and multi-modulus divider

Granted: March 8, 2016
Patent Number: 9281825
Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of…

Multi-level store merging in a cache and memory hierarchy

Granted: March 8, 2016
Patent Number: 9280479
A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the…

Processor hang detection and recovery

Granted: February 23, 2016
Patent Number: 9268627
Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record…

Reformating a plurality of signals to generate a combined signal comprising a higher data rate than a data rate associated with the plurality of signals

Granted: January 26, 2016
Patent Number: 9246617
Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined…

System and method for scaling total client capacity with a standard-compliant optical transport network (OTN)

Granted: January 5, 2016
Patent Number: 9231721
In an Optical Transport Network (OTN) system, methods and devices are provided for communicating rate-adaptive OTUk frames. One method determines channel statistics for a fiber span connecting a transmitter to a receiver. A client input data rate is determined that is sufficient to meet a minimum communication threshold, and a rate-adaptive OTUk frame format is determined sufficient to carry the client input data rate. The format comprises a set of (n) allocated slots of client input…

Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system

Granted: December 15, 2015
Patent Number: 9213643
Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

High speed transceiver based on embedded leech lattice constellation

Granted: October 27, 2015
Patent Number: 9172578
A transceiver architectures can comprises an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on a leech lattice. The data can be transmitted at a high speed according to the constellation with an embedded leech lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency…

Dynamic power control

Granted: October 27, 2015
Patent Number: 9170642
Systems and methods are provided that facilitate power management in a processing device. The system contains a power management component and a coupled to the processing device. The power management component determines and input rate and target voltages and/or frequency. The power management component can scale voltages and/or frequencies based on target voltages and/or frequencies. Accordingly, power consumption can be reduced and processing devices can be more efficient.

Packet processing with dynamic load balancing

Granted: October 13, 2015
Patent Number: 9158713
A system and method are provided for evenly distributing central processing unit (CPU) packet processing workloads. The method accepts packets for processing at a port hardware module port interface. The port hardware module supplies the packets to a direct memory access (DMA) engine for storage in system memory. The port hardware module also supplies descriptors to a mailbox. Each descriptor identifies a corresponding packet. The mailbox has a plurality of slots, and loads the…

System and method for searching a data structure

Granted: October 6, 2015
Patent Number: 9152661
System and method for searching a data structure are disclosed. The method includes providing a data structure that includes a plurality of data entries stored in an external random access memory (RAM) and a portion of the data structure is stored in an internal cache memory, performing one or more hash functions on each entry of the data structure to generate an encoding that maps to a location in the external RAM, maintaining a count of encodings that map to the location in the…

Systems and methods for queue request ordering without stalling requests in aliasing conditions by using a hash indexed based table

Granted: September 29, 2015
Patent Number: 9146677
The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In…

Integrated circuit memory device with read-disturb control

Granted: September 22, 2015
Patent Number: 9142286
A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a…

Imaging system for passive alignment of engines

Granted: July 21, 2015
Patent Number: 9088357
Methods and systems for facilitating alignment of optical systems and optoelectronic systems are disclosed here. The methods and systems include passively detecting images, determining relative positions of components and aligning components. An imaging component can detect images and determine relative positions and repositioning instructions.