Voltage Regulator Configuration
Granted: June 28, 2012
Application Number:
20120161732
A voltage regulator is configurable to operate in a linear regulator mode or a buck regulator mode. To operate in the buck regulator mode, the voltage regulator is coupled to an inductor. To determine whether an inductor is coupled to voltage regulator, and thus whether the voltage regulator can be configured in the buck regulator mode, a detection circuit determines whether a regulator output of the voltage regulator resists a change in current driven to the regulator output.
LOW-POWER OPERATION FOR DEVICES WITH CIRCUITRY FOR PROVIDING REFERENCE OR REGULATED VOLTAGES
Granted: June 28, 2012
Application Number:
20120161746
A device includes a voltage regulator and/or circuitry for generating a reference voltage. The voltage regulator and the circuitry for generating the reference voltage are operable in a continuous mode or a sample mode. Operating in the sample mode can help reduce overall power consumption of the device. During the sample mode, the voltage regulator and/or the circuitry for generating the reference voltage periodically are enabled to restore energy to respective energy storage components…
COMPENSATING DFLL WITH ERROR AVERAGING
Granted: June 28, 2012
Application Number:
20120161826
A compensating DFLL (CDFLL) is disclosed that utilizes temperature readings at regular intervals in combination with production characterization data of a reference oscillator to compensate for frequency drift and nominal frequency error. In some implementations, the CDFLL selects a calibration value that is not optimal for frequency accuracy to minimize accumulated frequency error over time. More particularly, during a calibration run, mismatch between an ideal frequency and an actual…
Operating a Transceiver
Granted: June 28, 2012
Application Number:
20120163424
In one embodiment, by a transceiver, setting a first receive frequency of a first channel of the transceiver and a second receive frequency of a second channel of the transceiver, during a first time interval, receiving a first radio frequency (RF) signal on the first channel, determining that a first measured value indicative of a first detectable received RF signal on the first channel exceeds a first predetermined threshold, and in response, receiving a first data frame on the first…
Measuring Sum of Squared Current
Granted: June 28, 2012
Application Number:
20120166506
A modulator can be configured to sense a change in current flow in a circuit and to generate an oversampled, noise-shaped signal. A first decimation filter is coupled to the modulator and is configured to generate instantaneous current data at a first data rate. The instantaneous current data can be input into a multiplier circuit. The output of the multiplier circuit (the instantaneous current data squared) can be input to a second decimation filter. The second decimation filter can be…
EVENT SYSTEM AND TIMEKEEPING FOR BATTERY MANAGEMENT AND PROTECTION SYSTEM
Granted: June 28, 2012
Application Number:
20120166841
Operating a battery management and protection system includes generating a set of events each of which has a respective frequency F/n1, F/n2 . . . F/nm, where ni are integers. One or more of the events are provided to one or more modules in the system. The events, which are generated and provided to the modules independently of a central processing unit, trigger performance of respective actions by the modules.
Verification of Configuration Parameters
Granted: June 28, 2012
Application Number:
20120166918
In a battery management system, error detection data is generated for various configuration parameters used by the battery management system. The error detection data is compared against corresponding error detection data previously generated during production or development of a battery pack or battery pack application. Based on the comparison, an appropriate action can be taken.
Semiconductor Package
Granted: June 28, 2012
Application Number:
20120161306
In one embodiment, a semiconductor package comprising a metal base coupled to one or more pins, a semiconductor body having a top side and a bottom side, the top side comprising an integrated circuit and one or more metal surfaces for coupling the integrated circuit to the one more pins with one or more bonding wires, the bottom side non-positively coupled to the metal base, a disk having a top area and a base area, the base area coupled to the top side of the semiconductor body and at…
SOFTWARE FRAMEWORK AND DEVELOPMENT PLATFORM FOR MULTI-SENSOR SYSTEMS
Granted: June 14, 2012
Application Number:
20120151432
The disclosed software framework and development platform facilitates software development for multi-sensor systems. In some implementations, developers can select a sensor board that includes a desired combination of sensor devices. The sensor board can be coupled to a development board that includes a target processor and other circuitry to facilitate development and testing of a system that includes the target processor and the sensors. Various software support tools are provided…
POSITION-SENSING AND FORCE DETECTION PANEL
Granted: June 7, 2012
Application Number:
20120139864
Disclosed is a touch position sensor. Force detection circuitry can be included with the position sensor, for example, to determine an amount of force applied to a touch panel of the sensor.
CHARGE INJECTION MECHANISM FOR ANALOG-TO-DIGITAL CONVERTERS
Granted: June 7, 2012
Application Number:
20120139767
A low-cost charge injection mechanism may enable oversampling to be used on low frequency signals by injecting dither noise into the ADC input. The dither noise can reduce the quantization noise allowing even direct current (DC) signals to be oversampled correctly. A low-cost charge injection mechanism can also be used to improve the ENOB by characterizing the ADC and digitally correcting the converted signal for non-linearity errors such as INL. Reducing INL errors may also allow a…
NON-VOLATILE MEMORY COUNTER
Granted: May 17, 2012
Application Number:
20120121060
A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write…
METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES
Granted: May 3, 2012
Application Number:
20120106250
Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a…
Communication Protocol Method And Apparatus For A Single Wire Device
Granted: April 26, 2012
Application Number:
20120099662
The present invention is a noise tolerant communication protocol device and method where a clock signal input, triggers an internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during…
Error Detecting/Correcting Scheme For Memories
Granted: April 19, 2012
Application Number:
20120096334
A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR…
Charge Equalization Between Series-Connected Battery Cells
Granted: March 29, 2012
Application Number:
20120074895
In one embodiment, a method includes receiving a first input current from a battery through a first connection and a second connection and generating a first output current through a third connection to a first node and a fourth connection to a second node. The first and second nodes are configured to output the first output current to an energy store configured to store a charge. The method includes receiving a second input current through the third connection from the first node and…
Charge Equalization Between Series-Connected Battery Cells
Granted: March 29, 2012
Application Number:
20120074907
In one embodiment, a circuit comprising a first set of one or more semiconductor switches coupled to a first node and a first terminal of an energy store configured to store energy, and a second set of one or more semiconductor switches coupled to a second node and a second terminal of the energy store, each of the first and second sets of semiconductor switches being configured to couple to a terminal of a battery cell.
Frequency Locking Oscillator
Granted: March 22, 2012
Application Number:
20120068775
A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.
Transmitting/Receiving Device and Method for Transmitting Data in a Radio Network
Granted: March 15, 2012
Application Number:
20120064842
In one embodiment, a method includes receiving an instruction for a transceiver of a device to transmit a first data frame; in response to the instruction, generating a first control signal for a switch to couple the transceiver to a first antenna for transmission of the first data frame by the transceiver via the first antenna; determining whether the transceiver has received within a pre-determined time interval after the transmission of the first data frame a second data frame…
PROCESSOR INDEPENDENT LOOP ENTRY CACHE
Granted: March 8, 2012
Application Number:
20120059975
A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a…
