Voltage regulator for an integrated circuit
Granted: February 14, 2012
Patent Number:
8115462
A voltage regulator is disclosed. The voltage regulator includes a comparator for providing a gated output signal; and a state machine for receiving the gated output signal. The voltage regulator further includes at least one switch cell controlled by the state machine, for delivering charge to a load. Accordingly, a voltage regulator in accordance with the present invention yields N times (where N is an integer greater than one) the linear efficiency over typical linear regulators…
Method for data communication between a base station and a transponder
Granted: February 7, 2012
Patent Number:
8111672
A method for wireless data communication between a base station and at least one transponder by a high-frequency electromagnetic carrier signal, onto which information packets are modulated, wherein each information packet has a header section, a middle section, and a terminating end section, wherein the middle section has a data field, which contains the data necessary for the data communication, wherein at least one additional control field is inserted into the data field by which the…
Error detecting/correcting scheme for memories
Granted: February 7, 2012
Patent Number:
8112699
A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR…
Differential detection unit for the zigbee 802.15.4 standard
Granted: January 31, 2012
Patent Number:
8107513
In one embodiment, a detection unit includes a sequence providing unit to provide a third group of derived sequences. The sequence providing unit has a counting unit and multiplexers connected to the counting unit. Fixed values are applied at the inputs of the multiplexers and the sequence providing unit provides the derived sequences of the third group at the outputs of the multiplexers. The third group for each first pseudo noise (PN) sequence has a derived sequence assigned to the…
Communication protocol method and apparatus for a single wire device
Granted: January 31, 2012
Patent Number:
8107577
The present invention is a noise tolerant communication protocol device and method where a clock signal input triggers an internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during…
Signal processing device and signal processing method
Granted: January 31, 2012
Patent Number:
8107911
A signal processing device and signal processing method is provided that includes a detection unit for detecting a signal strength of a signal, whereby the detection unit is configured to output a detection value that represents the signal strength of the signal; a settable digital filter connected upstream of the detection unit, whereby filter coefficients for setting a transfer characteristic of the filter are assigned to an amplification or attenuation of the signal by the filter; a…
Circuit and method for operating a circuit
Granted: January 24, 2012
Patent Number:
8101900
A circuit and method for operating a circuit with a terminal for connecting a photodiode to output an output current dependent on the photocurrent of the photodiode, with a resistance device for generating a voltage drop dependent on a photocurrent of the photodiode, with a control loop connected to the resistance device for generating the output current dependent on the photocurrent, with a switching means connected to the terminal with first switch positions for a first operating mode…
Capacitive keyboard with non—locking reduced keying ambiguity
Granted: January 24, 2012
Patent Number:
8102286
Keyboards, keypads and other data entry devices can suffer from a keying ambiguity problem. In a small keyboard, for example, a user's finger is likely to overlap from a desired key to onto adjacent ones. An iterative method of removing keying ambiguity from a keyboard comprising an array of capacitive keys involves measuring a signal strength associated with each key in the array, comparing the measured signal strengths to find a maximum, determining that the key having the maximum…
Display controller operating mode using multiple data buffers
Granted: January 24, 2012
Patent Number:
8102401
A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of registers. A set of multiplexers has first data inputs coupled to the first set of registers, second data inputs coupled to the second set of registers, and select inputs. Logic circuitry is coupled to the output of the set of multiplexers and to the control inputs of the multiplexers, the…
Security method for data protection
Granted: January 17, 2012
Patent Number:
8099783
An integrated circuit (IC) security apparatus with complementary security traces and a method for producing such an apparatus is disclosed. The security apparatus comprises a pattern generator, and a plurality of security traces. The arrangement of security trace pairs are such that the second trace is arranged substantially parallel to the first trace. The pattern generator produces two signals, a second signal, which is applied to the second trace, is substantially complimentary to the…
Simulation model for transistors
Granted: January 17, 2012
Patent Number:
8099270
Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model.
Method and system for incorporating high voltage devices in an EEPROM
Granted: January 10, 2012
Patent Number:
8093640
A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and…
Snap-back tolerant integrated circuits
Granted: December 27, 2011
Patent Number:
8085604
A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar transistor. A second NMOS transistor may be connected in series with the first NMOS transistor. A gate node of the second NMOS transistor may be coupled to a bias node, such that the second NMOS transistor in conductive (ON)…
MOS resistor with second or higher order compensation
Granted: November 29, 2011
Patent Number:
8067975
A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit…
Method and system for minimizing the accumulated offset error for an analog to digital converter
Granted: November 15, 2011
Patent Number:
8059019
A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then…
ROM array with shared bit-lines
Granted: November 15, 2011
Patent Number:
8059442
Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.
Communication method in RFID or remote sensor systems
Granted: November 8, 2011
Patent Number:
8054162
A method for communicating between a control unit and a plurality of remote units located in the response area of the control unit is provided. The remote units are prompted to transmit a data sequence to the control unit upon receipt of a command sent by the control unit. The control unit transmits a control signal to the remote units substantially simultaneously with the transmission of the data sequence as a function of a communication state, such as the absence of a transmission of…
Voltage generator for memory array
Granted: November 8, 2011
Patent Number:
8054694
A high voltage may be generated for programming memory cells in a memory array. A middle voltage may also be generated for reading memory cells in the memory array. Control logic and switches may be used to select between the high voltage and the middle voltage. A first oscillator generates clock signals at a high frequency for generating the voltages, and a low frequency oscillator may be used to generate pulses at a lower frequency than the first oscillator to allow the first…
Method for edge formation of signals and transmitter/receiver component for a bus system
Granted: November 8, 2011
Patent Number:
8054911
A method is provided for edge formation of signals and transmitter/receiver component for a bus system. A transmitter/receiver component for a bus system comprises a driver transistor, which is to be looped between a bus line of the bus system and a reference potential and is used to output signals on the bus line, a control unit for the driver transistor, a high-frequency interference detector, which is configured in such a way that it detects a high-frequency interference level on the…
Accessing sequential data in a microcontroller
Granted: November 8, 2011
Patent Number:
8055963
System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.
