Comparator chain offset reduction
Granted: April 1, 2008
Patent Number:
7352307
Comparator chain total offset, static and dynamic, is reduced by injecting a compensation quantity in at least one point in the chain of comparator components. The compensation quantity is determined by providing the comparator chain with calibration signals having equal values and evaluating the output states of the comparator chain. The compensation quantity is adjusted until the probabilities of high and low output states are substantially equal and a calibrated value for the…
High-speed, self-synchronized current sense amplifier
Granted: April 1, 2008
Patent Number:
7352640
A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to…
Apparatus to improve the firmware efficiency for a multiframe serial interface
Granted: April 1, 2008
Patent Number:
7353300
A serial network controller contains control logic to analyze and determine a duration of a proper frame time slot. A number of data fields in a transmission is ascertained from an identifier field supplied in a header field. The number of data fields plus a margin for data framing overhead is calculated to determine the frame time slot duration. A timer is programmed with the calculated frame time slot duration. The timer is clocked at each bit period of the transmission until the…
Microcontroller with synchronised analog to digital converter
Granted: April 1, 2008
Patent Number:
7353417
A microcontroller is provided, which includes a control unit (UC), at least one digital to analog converter (DAC) as a peripheral of the said control unit, and a buffer register located between the said control unit and the said converter, receiving data and a first command to transfer the said data from the said control unit. The microcontroller includes means of synchronisation of the said converter including a register inserted between the said buffer register and the said converter,…
Device for comparing two words of n bits each
Granted: April 1, 2008
Patent Number:
7352275
The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=i=n?1. Moreover, each basic comparator block comprises: a first sub-block which can be used to generate a first signal indicating whether or not bits Ni and Pi are equal, said signal being generated at the output of the…
Process for manufacturing a semiconductor device, a semiconductor device and a high-frequency circuit
Granted: March 25, 2008
Patent Number:
7348221
A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding from the open, monocrystalline semiconductor region, acting as a crystallization nucleus, so that the silicide layer is covered at…
Methods of forming reduced electric field DMOS using self-aligned trench isolation
Granted: March 25, 2008
Patent Number:
7348256
A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding…
Method of making nonvolatile transistor pairs with shared control gate
Granted: March 25, 2008
Patent Number:
7348626
A pair of nonvolatile memory transistors are carved from a single polysilicon floating gate on an insulated substrate. After surrounding the poly floating gate with insulator, the poly is etched except for two remnants remaining on lateral sides of the original floating gate. These remnants become a pair of new floating gates for the transistor pair. Prior to etching of the poly, the poly may be used for self-aligned placement of highly doped regions that serve as electrodes for the two…
Integrated circuit with automatic start-up function
Granted: March 25, 2008
Patent Number:
7348830
The invention relates to integrated electronic circuits, and notably to those comprising analog functions. The invention relates more particularly to a starter circuit designed to ensure the automatic start-up of a biasing circuit following an interruption in the operation of the latter. The starter circuit comprises, in an integrated circuit substrate of a first type of conductivity comprising at least one well of an opposite type of conductivity and a semiconductor region of the same…
Common mode management between a current-steering DAC and transconductance filter in a transmission system
Granted: March 25, 2008
Patent Number:
7348911
Common mode management between a DAC, such as a current-steering DAC, and a transconductance filter in a high-frequency transmission system. In one aspect of the invention, a transmission circuit includes a DAC that provides an analog signal from an input digital signal, and a filter such as a transconductance filter connected to the DAC, the filter receiving the analog signal and filtering the analog signal for transmission. A common mode management circuit connected to the DAC and the…
Driver circuit with automatic offset compensation of an amplifier and method for offset compensation of an amplifier of a driver circuit
Granted: March 18, 2008
Patent Number:
7345513
A driver circuit is provided, which includes a differential amplifier whose output signal controls the driving input signal, a reference signal generator that supplies a reference input of the differential amplifier, an external feedback that applies a signal, which is dependent on the output signal, to a feedback input of the differential amplifier, an adapter circuit, and an internal feedback activated in a compensation mode as an alternative to the external feedback, which internal…
Method and system for a programming approach for a nonvolatile electronic device
Granted: March 18, 2008
Patent Number:
7345921
Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
Method of making EEPROM transistor pairs for block alterable memory
Granted: March 11, 2008
Patent Number:
7341911
A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain implant region. A tunnel oxide layer overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. A first oxide layer overlies the tunnel oxide layer, with an inter poly layer overlying the…
Self-aligned nanometer-level transistor defined without lithography
Granted: March 11, 2008
Patent Number:
7341916
A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.
Component stacking for integrated circuit electronic package
Granted: March 11, 2008
Patent Number:
7342308
Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the…
Method and circuit arrangement for wireless data transmission
Granted: March 11, 2008
Patent Number:
7342481
A method and circuit for wireless data transmission between a base station and one or more transponders is provided in which the base station modulates a carrier signal with a modulation signal and transmits it, in which symbols that are to be transmitted are coded by the base station using sequential delimiters. A value of a particular symbol being determined by the time period between two sequential delimiters, and in which the particular delimiter is generated by changing the…
Method of fabricating a semiconductor device having a toroidal-like junction
Granted: March 4, 2008
Patent Number:
7338875
Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot…
Voltage-controlled oscillator with multi-phase realignment of asymmetric stages
Granted: March 4, 2008
Patent Number:
7339439
A multi-phase realigned voltage-controlled oscillator (MRVCO) achieves phase realignment based on charge injection in the VCO stages. The individual VCO stages provide an oscillating output signals having an asymmetric waveform with substantially different rise and fall times. This ensures that the VCO as a whole has a multiphase impulse response to the charge injection that is strictly positive or strictly negative, and substantially constant so as to be independent of the VCO phase or…
Array source line (AVSS) controlled high voltage regulation for programming flash or EE array
Granted: March 4, 2008
Patent Number:
7339832
A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential VAVSS of an array VSS line by means of a comparator, allowing the array VSS line to electrically float until the potential VAVSS is approximately equal to a reference potential Vref, and terminating the programming by de-coupling at least one of the current source and the potential source.
Method and apparatus of temperature compensation for integrated circuit chip using on-chip sensor and computation means
Granted: March 4, 2008
Patent Number:
7340366
A method and apparatus of temperature compensation for an integrated circuit using on-chip circuits, sensors, and an algorithm. The chip includes an on-chip reference circuit, an on-chip sensor measuring a parameter relative to the reference, and an on-chip computation means for processing an algorithm. A supplemental off-chip reference circuit is also used. The algorithm carries out the following steps: (A) performing a first calibration of an internal reference residing in an…
