High voltage tolerant port driver
Granted: February 26, 2008
Patent Number:
7336109
A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. A high-voltage tolerant driver includes a plurality of output drive devices capable of…
Differential amplitude controlled sawtooth generator
Granted: February 26, 2008
Patent Number:
7336110
A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawtooth voltage generator has a first discharge capacitor and a second discharge capacitor that are alternately discharged with a feedback control sink current from a high voltage reference voltage level. The output signals of the…
Method for selecting one or more transponders
Granted: February 26, 2008
Patent Number:
7336154
One or more transponders are selected by a base station out of a plurality of transponders. For this purpose an identification bit sequence (IB) that is or includes a random number bit sequence (ZB) is made available in the respective transponder and the base station transmits in a bit-by-bit fashion a selection bit sequence (AB) to the transponders. These sequences (IB or ZB) and (AB) are compared bit-by-bit in the respective transponder. The comparing is performed by way of a…
Indirect measurement of negative margin voltages in endurance testing of EEPROM cells
Granted: February 26, 2008
Patent Number:
7336540
An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a…
Nonvolatile latch
Granted: February 26, 2008
Patent Number:
7336542
A nonvolatile latch includes a memory element for storing an input data value. A write protect element is coupled to the memory element for utilizing a write protect signal to ensure the input data value stored by the memory element remains during a loss of a supply voltage to the latch.
Ultrascalable vertical MOS transistor with planar contacts
Granted: February 26, 2008
Patent Number:
7335943
A doped silicon block or island, formed above a drain electrode in substrate of a die or chip, has a height corresponding to the desired length of a channel. A source electrode is formed above the silicon island and allows for contact from above. Contact from above may also be made with an L-shaped control gate and with the subsurface drain. A horizontal array of contacts for source, gate and drain is formed for the vertical transistor that is built. If a layer of nanocrystals is…
Column decoding architecture for flash memories
Granted: February 19, 2008
Patent Number:
7333389
An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a…
Receiver circuit and method using selectively variable amplification for receiving time signals from different transmitters
Granted: February 19, 2008
Patent Number:
7333467
A time signal carrying encoded time information transmitted at a transmission frequency from any one of plural time signal transmitters is received, amplified, and evaluated to acquire the time information. The transmission frequency of the received time signal is determined (provided is the time information signal's just emitted frequency f), and an amplification factor of the amplification of the signal is adjusted depending on the transmission frequency. A receiver circuit for a…
Sense amplifier circuit for parallel sensing of four current levels
Granted: February 12, 2008
Patent Number:
7330375
A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, and a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline. To sense multiple current levels and multiple stored bits per memory cell, multiple direct current amplification circuits are electrically coupled to the sensing circuit for amplifying the current sensed on the bitline, multiple current-to-voltage conversion circuits for converting…
Charge pump clock for non-volatile memories
Granted: February 5, 2008
Patent Number:
7327171
A charge pump clock circuit for a memory device generates pump clock signals at an adaptive rate. Clock edges are generated at a minimum of TD seconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*TD), then clock edges will be generated at a rate that is proportional to the rate of address changes, where TD is approximately half of the address period. Two logic rules are…
Interface for compressed data transfer between host system and parallel data processing system
Granted: February 5, 2008
Patent Number:
7328299
An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiver with selectable device interface modes. When operating as a transmitter, the interface apparatus combines and compresses the system data bus, clocks, and control signals to match the available width of the parallel data…
Apparatus and method incorporating discrete passive components in an electronic package
Granted: February 5, 2008
Patent Number:
7327030
An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic processing, a pattern is formed with the photosensitive material to expose at least one region of the metal layer. The remaining photosensitive material protects the underlying metal during metal etching. The substrate is then…
Plug connector modules of a plug connector for simultaneously connecting a plurality of electrical contacts
Granted: January 29, 2008
Patent Number:
7322837
A first plug connector module of a plug connector for substantially simultaneously connecting a plurality of electrical contacts between a test signal generator and a measurement card of a handling fixture which delivers elements to be tested to the measurement card. The plug connector module is characterized in that it has an element that is rotatable about an axis of rotation and has, coupled to the rotatable element, a receptacle that accommodates a mating part of a second plug…
Die attach paddle for mounting integrated circuit die
Granted: January 29, 2008
Patent Number:
7323765
An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the…
Power efficient startup circuit for activating a bandgap reference circuit
Granted: January 29, 2008
Patent Number:
7323856
A power efficient startup circuit for activating a bandgap reference circuit is disclosed. The startup circuit uses a voltage supply having a voltage level to initiate the flow of a startup current used to activate the bandgap reference circuit. When the bandgap reference circuit starts, the startup circuit slowly charges a capacitor using the voltage supply when the startup current is flowing. The startup circuit disables quiescent current when the bandgap reference circuit is activated…
Selectable block protection for non-volatile memory
Granted: January 29, 2008
Patent Number:
7325114
A semiconductor non-volatile memory device, particularly a flash memory array, having a chip configuration with a plurality of pins including a write protect pin, a serial in pin and an optional parallel data bus with input-output pins (I/O7-0), plus other pins, all electrically communicating with the memory array and particularly a sector protection register of variable size and location. The sector protection register defines which sectors or group of sub-sectors to protect and is…
Integrated circuit and method for manufacturing an integrated circuit on a semiconductor chip
Granted: January 22, 2008
Patent Number:
7320922
An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second bipolar transistor has a second collector region of this first conductivity type grown by this epitaxial layer. The first collector region also has a first collector drift zone, and the second collector region has a second…
Security device for a transponder
Granted: January 22, 2008
Patent Number:
7321300
A security device for a transponder with a kill and/or cloak function is provided. The security device includes a memory device, in which a first, open password is stored, an input, into which a second, secret password is coupled, a cryptologic device, which is connected to the input and generates a checksum from the second password, and a comparison unit, which compares the checksum and the first password and which upon an agreement generates a kill and/or cloak control instruction to…
Method and circuit arrangement for load modulation in a combination comprised of a transmitting and a receiving oscillator circuit
Granted: January 15, 2008
Patent Number:
7319368
A method and circuit arrangement is provided for load modulation in a receiving oscillator circuit, which can be mutually coupled with a transmitting oscillator circuit, having at least one inductance, at least one capacitance, and at least one controllable impedance. The controllable impedance can have at least one depletion layer element and at least one ohmic resistance.
Circuit arrangement for load regulation in the receive path of a transponder
Granted: January 8, 2008
Patent Number:
7317307
A circuit arrangement for load regulation of circuit components is arranged in a receive path of a transponder, having an input path through which a first voltage signal can be tapped, having a voltage sensor arranged in the input path for measuring the first voltage signal, having at least one output path through which a discharge current signal can be tapped, having at least one controllable auxiliary current source arranged between the input path and the output path to provide the at…
