Radio-controlled clock and method for gaining time information
Granted: January 8, 2008
Patent Number:
7317905
Time signals for controlling a radio clock are transmitted by a transmitter and received by a receiver as amplitude modulated time signals, formed of a multitude of time frames. Each time frame has a constant duration. These time signals are first automatically amplified. A so-called telegram of at least one received time signal is stored in a memory. At least one change of an amplitude of a time signal is determined in advance or predetermined and such amplitude change has a duration…
Nonvolatile semiconductor memory apparatus
Granted: January 8, 2008
Patent Number:
7317630
A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A…
Integrated multisensor
Granted: January 1, 2008
Patent Number:
7313950
An integrated multisensor, in particular for use in an internal combustion engine of a motor vehicle is provided. The multisensor includes at least one pressure/temperature sensor, at least one magnetic field sensor, and a plurality of insulating wells, wherein a separate insulating well encloses each pressure/temperature sensor or magnetic field sensor such that the sensors are each electrically and mechanically decoupled from one another.
Method for frequency conversion and receiver
Granted: January 1, 2008
Patent Number:
7315732
A method and device for frequency conversion is disclosed in which a first signal with a first frequency is converted into a second frequency through mixing with a divided oscillator signal and wherein the frequency of the divided oscillator signal stands in a fractional rational ratio to the frequency of the undivided oscillator signal. The method is characterized in that the oscillator signal is divided such that an average value of the divided oscillator signal over time corresponds…
Power failure detection circuit with fast drop response
Granted: December 25, 2007
Patent Number:
7312644
A device is provided for resetting an integrated circuit generating a reset signal after a power supply voltage drop to a very low level has been detected. Such a device includes at least one control means, the state of which (conducting or non-conducting) is controlled by a control voltage equal to the difference between the power supply voltage and a predetermined offset voltage, such that if the control voltage is less than or equal to a threshold, the control means authorizes…
Method for selecting one or several transponders
Granted: December 25, 2007
Patent Number:
7312692
In a method for selecting, by a base station, one or more transponders out of a plurality of transponders, selection steps are performed at least at two selection levels or stages. The base station controls all selection steps at the first and second level. The first selection level includes: each transponder generates a random transponder number, the base station generates numbered time slots, each transponder transmits a marker if and when its random transponder number coincides with a…
Method for producing a coplanar waveguide system on a substrate, and a component for the transmission of electromagnetic waves fabricated in accordance with such a method
Granted: December 11, 2007
Patent Number:
7307497
A component for the transmission of electromagnetic waves and a method for producing such a component is provided, whereby conductors of a coplanar waveguide system are embedded in a membrane such that they are at least partially suspended across a back-etched area of the substrate for the decoupling of the conductors from the substrate (1). An additional substrate is connected to the bottom side of the back-etched area of the substrate in such a way that a hollow cavity is formed.
Method and apparatus for implementing walkout of device junctions
Granted: December 11, 2007
Patent Number:
7307898
A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third…
Bi-directional serial interface for communication control
Granted: December 11, 2007
Patent Number:
7308516
A bi-directional serial interface for serial communication having a control line to facilitate the transmission of data to and from a microcontroller and a serial interface module. The control line can be used by both the microcontroller and the serial interface module to send controlling signals such as start signals, receipt acknowledge signals, error signals, and stop signals. By having a dedicated control line that can be used by both the sending device and the receiving device, the…
Autonomous antifuse cell
Granted: December 4, 2007
Patent Number:
7304878
An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent…
Fast read port for register file
Granted: December 4, 2007
Patent Number:
7304904
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired…
Double byte select high voltage line for EEPROM memory block
Granted: December 4, 2007
Patent Number:
7304890
A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between…
Methods and circuits for sensing on-chip voltage in powerup mode
Granted: December 4, 2007
Patent Number:
7304514
A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input…
Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement
Granted: November 27, 2007
Patent Number:
7300849
A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; forming a cap layer overlying the compound base region including doping the cap layer with a pre-determined percentage of at least one element associated with the compound base region; and forming an emitter region over the cap layer.
Non-volatile nanocrystal memory transistors using low voltage impact ionization
Granted: November 27, 2007
Patent Number:
7301197
A low voltage non-volatile charge storage transistor has a nanocrystal layer for permanently storing charge until erased. A subsurface charge injector generates secondary carriers by stimulating electron-hole current flowing toward the substrate, with some carriers impacting charge in nanocrystals. The charge injector is a p-n junction diode where one polarity is source and drain electrodes and the other polarity is two split doped regions in the substrate partially overlapping the…
Non-volatile memory array with simultaneous write and erase feature
Granted: November 27, 2007
Patent Number:
7301794
A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has current injectors ready to operate if program line voltages are appropriate to cause charge storage in a memory cell, while a cell in an adjacent row be erased by charge being driven from a…
System and method for avoiding offset in and reducing the footprint of a non-volatile memory
Granted: November 27, 2007
Patent Number:
7301814
A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current…
Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
Granted: November 27, 2007
Patent Number:
7301832
A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. Redundant memory cells are accessed by use of column redundancy information output from the content addressable memory. During a memory access cycle a register in the content addressable memory latches a memory address. The…
Method and system for managing a suspend request in a flash memory
Granted: November 27, 2007
Patent Number:
7302518
System and method for the managing of suspend requests in flash memory devices. The system includes a microcontroller performing a modify operation on a flash memory array, a memory coupled to the microcontroller and storing suspend sequence code for causing a suspension of the modify operation when executed by the microcontroller, and suspend circuitry that receives a suspend request from a user to suspend the modify operation and starts the execution of the suspend sequence code.
Power down detection circuit
Granted: November 13, 2007
Patent Number:
7295046
A power down reset circuit for asserting a signal when a first VDD voltage falls below a voltage threshold. The circuit has at least one diode coupled to the first VDD voltage. The at least one diode is configured to produce a second voltage. At least one capacitor is coupled to the at least one diode to maintain the second voltage. A voltage detector asserts a signal when the first VDD voltage drops below a threshold level. The voltage detector is powered by the second voltage and is…
