INPUT/OUTPUT MULTIPLEXER BUS
Granted: April 1, 2021
Application Number:
20210096164
One embodiment includes and I/0 bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/0 port to the signal line. Switch logic coupled to the I/0 bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/0 port.
DETECTION OF VARIATION IN LOAD IMPEDANCE OF WIRELESS COMMUNICATIONS DEVICES
Granted: March 25, 2021
Application Number:
20210091867
Systems, methods, and devices detect variations in load impedances of wireless communications devices. Methods include determining a first distortion measurement of a transceiver based on a first comparison of a digital loopback path and a radio frequency (RF) loopback path, and determining a second distortion measurement of the transceiver based on a second comparison of the digital loopback path and the RF loopback path. Methods also include implementing, using a processor, a third…
METHOD AND APPARATUS FOR DATA TRANSMISSION VIA CAPACITANCE SENSING DEVICE
Granted: March 25, 2021
Application Number:
20210091823
A system made up of a first device which includes a communication interface and a processing device and a second device which includes a touch sensor assembly and a controller, where the controller uses the touch sensor assembly to communicate with the processing device through a capacitor that is jointly formed by the touch sensor assembly and a conductive portion of the communications interface.
POWER-EFFICIENT SYNC-RECTIFIER GATE DRIVER ARCHITECTURE
Granted: March 25, 2021
Application Number:
20210091675
A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate…
AVOIDING FALSE NSN DETECTION IN FLYBACK CONVERTERS
Granted: March 25, 2021
Application Number:
20210091654
Techniques for avoiding false negative sense (NSN) detection in a flyback AC-DC converter are described herein. In an example embodiment, a secondary side controller of the AC-DC converter comprises a frequency detector, a negative sense detector, and control logic. The frequency detector is configured to determine a frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sense detector is…
Memory First Process Flow and Device
Granted: March 25, 2021
Application Number:
20210091198
A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure.…
USB TYPE-C SIGNAL INTERFACE CIRCUIT
Granted: March 25, 2021
Application Number:
20210089100
A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger…
SYSTEM LEVEL SIMULATION AND EVALUATION OF CAPACITIVE AND INDUCTIVE SENSING-BASED SOLUTIONS
Granted: March 18, 2021
Application Number:
20210081590
Information associated with a plurality of components of a capacitance sensing system is received. Performance of the capacitance sensing system is simulated based on the information associated with the plurality of components of the capacitance sensing system. A set of configuration parameters for a capacitance sensing controller is generated without user intervention based on the simulated performance of the capacitance sensing system.
SYSTEM AND METHODS FOR LOW POWER CONSUMPTION BY A WIRELESS SENSOR DEVICE
Granted: March 18, 2021
Application Number:
20210083715
An example system and method operate a wireless device in a first mode with power to operate a communication resource of the wireless device at a first level. While operating the wireless device in the first mode, the system and method evaluates an attribute in a first portion of sensor data. Responsive to the evaluation of the attribute, the system and method transitions to the wireless device to operate in a second mode with power to operate the communication resource at a second…
NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME
Granted: March 18, 2021
Application Number:
20210082927
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the…
RADAR DETECTION IN A WIRELESS LAN
Granted: March 18, 2021
Application Number:
20210080535
Disclosed are methods and systems for a WLAN device operating on DFS channels to calibrate the PRI as well as delays between partial pulses of received radar pulses that are impaired due to channel and filtering effects. The calibrated PRI may approximate the PRI of the transmitted pulses. The calibrated delay between the partial pulses estimates the interval between two partial pulses that originally belong to the same transmitted pulse. Using the calibrated PRI and the calibrated delay…
Microwave Oven Coexistence with Wi-Fi/BT
Granted: March 4, 2021
Application Number:
20210068118
A wireless communication device and method for operating the same for mitigating interference in a wireless communication network are provided. Generally, the method includes sensing with the wireless communication device pulses of electromagnetic radiation recurring within a band of frequencies used by the device for communication of signals, identifying the pulses as interference, and determining a number of frequencies of the interference within the band of frequencies used by the…
BIT ERROR CORRECTION FOR WIRELESS RETRANSMISSION COMMUNICATIONS SYSTEMS
Granted: February 25, 2021
Application Number:
20210058190
Systems, methods, and apparatus receive a corrupted packet of an original packet and at least one corrupted retransmitted packet of the original packet and generate a decision packet for the original packet based on identical bits of the original packet received through the corrupted packet and the at least one corrupted retransmitted packet. Embodiments verify the decision packet to determine whether the decision packet is correct based on a last one of the at least one corrupted…
CONTROLLED GATE-SOURCE VOLTAGE N-CHANNEL FIELD EFFECT TRANSISTOR (NFET) GATE DRIVER
Granted: February 25, 2021
Application Number:
20210058005
Controlling gate-source voltage with a gate driver in a secondary-side integrated circuit (C) controller for a secondary-controlled AC-DC converter is described. In an example embodiment, the gate driver is configured to programmably control the gate-source voltage and the slew rate of a secondary-side provider field effect transistor (FET) in the converter.
SECONDARY-CONTROLLED ACTIVE CLAMP IMPLEMENTATION FOR IMPROVED EFFICIENCY
Granted: February 25, 2021
Application Number:
20210058000
Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.
ASSET LOCATION USING DIRECTION FINDING FEATURES
Granted: February 25, 2021
Application Number:
20210055366
Systems, methods, and apparatus cause a first wireless device to transmit to a plurality of locator devices, an extended signal including a first segment and second segment. The first segment includes an indication for each of the plurality of locator devices to listen for a change in the extended signal from the first segment to the second segment. The second segment includes an indication for each of the plurality of locator devices to rotate through a plurality of antennas to receive…
ESTIMATING ANGLE MEASUREMENTS FOR SOURCE TRACKING USING A PHASED ARRAY SYSTEM
Granted: February 11, 2021
Application Number:
20210041552
Example apparatus, systems and methods use a receiver of a first device to receive from a second device, radio frequency (RF) signals. Embodiments use a processor of the first device to determine, based on the RF signals, a set of angle-estimation values of an angle between a plurality of antenna elements of one of the first device and the second device and an antenna element of the other of the first device and the second device, and a set of confidence measurements. Each of the set of…
MULTI-PORTED NONVOLATILE MEMORY DEVICE WITH BANK ALLOCATION AND RELATED SYSTEMS AND METHODS
Granted: February 11, 2021
Application Number:
20210042245
A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in…
MEMORY CONTROLLER FOR NON-INTERFERING ACCESSES TO NONVOLATILE MEMORY BY DIFFERENT MASTERS, AND RELATED SYSTEMS AND METHODS
Granted: February 11, 2021
Application Number:
20210042054
A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device…
DETECTING THE ANGLE OF A TOUCH SCREEN MOUNTED PASSIVE DIAL
Granted: February 11, 2021
Application Number:
20210041977
A touch screen display and corresponding devices and methods are disclosed, the touch screen display comprising a touchscreen having a plurality of capacitive sensors and a passive dial having one or more conductive elements, the passive dial mounted within an active area of the touchscreen such that the one or more conductive elements are proximate to the face of the touchscreen and move in conjunction with a rotation of the passive dial. The touch screen display may further include a…
