DEVICES, SYSTEMS AND METHODS FOR CONNECTING AND AUTHENTICATING LOCAL DEVICES TO COMMON GATEWAY DEVICE
Granted: September 12, 2019
Application Number:
20190281455
A method can include detecting local devices with a wireless first communication interface (IF) of a gateway device; authenticating at least one local device with the gateway device, including by operation of the first communication IF and a second communication IF, relaying secure communications between the at least one local device and a server to enable authentication of the at least one local device by the server, and after receiving authentication of the at least one local device at…
SECURE BLE JUST WORKS PAIRING METHOD AGAINST MAN-IN-THE-MIDDLE ATTACK
Granted: September 12, 2019
Application Number:
20190281449
A method includes transmitting one or more segments of a security certificate on a wireless advertising channel of a peripheral device, where at least one of the segments of the security certificate identifies an authentication server, participating in a public key exchange between the peripheral device and a host device by transmitting a signed public key of the peripheral device, where the signed public key is signed in the security certificate, and transmitting one or more encrypted…
Suppression of Program Disturb with Bit Line and Select Gate Voltage Regulation
Granted: September 12, 2019
Application Number:
20190279729
Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage,…
FERROELECTRIC RANDOM ACCESS MEMORY SENSING SCHEME
Granted: September 12, 2019
Application Number:
20190279702
Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically…
DUAL PIPELINE ARCHITECTURE FOR WAKEUP PHRASE DETECTION WITH SPEECH ONSET DETECTION
Granted: September 12, 2019
Application Number:
20190279641
A phrase detection device includes a high latency pipeline to transmit a first portion of audio data from an audio data source to a processing unit, where the high latency pipeline includes a history buffer to store the first portion of the audio data, and a low latency pipeline to transmit a second portion of the audio data from the audio data source to the processing unit with a lower latency than the high latency pipeline. A sound onset detector coupled with the audio data source…
PROGRAMMABLE VBUS DISCHARGE IN USB POWER DELIVERY
Granted: September 12, 2019
Application Number:
20190278731
Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently…
SYSTEM AND METHODS FOR LOW POWER CONSUMPTION BY A WIRELESS SENSOR DEVICE
Granted: August 22, 2019
Application Number:
20190260413
An example system and method operate a wireless device in a first mode with power to operate a communication resource of the wireless device turned off. While operating the wireless device in the first mode, the system and method detects a voice attribute in a first portion of audio data, the audio data based on microphone input. Responsive to the detection of the voice attribute, the system and method transitions to the wireless device to operate in a second mode with power to operate…
TWO-ELECTRODE TOUCH BUTTON WITH A MULTI-PHASE CAPACITANCE MEASUREMENT PROCESS
Granted: July 25, 2019
Application Number:
20190227669
A method, apparatus, and system to detect whether a two-electrode touch button is pressed using a first self-capacitance measurement of an inner electrode of the two-electrode touch button and a second self-capacitance measurement of an outer electrode of the two-electrode touch button. The method, apparatus, and system further to detect whether the two-electrode touch button is pressed in view of presence of water proximate to the touch button.
DUAL ADVANCED AUDIO DISTRIBUTION PROFILE (A2DP) SINK
Granted: July 25, 2019
Application Number:
20190230459
Wireless communication schemes and techniques are described, wherein a secondary device is configured to eavesdrop information communicated between a source and a primary device. Secondary device transmits a NACK signal to jam ACK signals from the primary device to the audio source, forcing a retransmit of audio information from the source to the primary, and available over an eavesdropping link between the secondary device and the source.
Configurable bus
Granted: July 25, 2019
Application Number:
20190227818
A device includes an analog block array, a first analog bus segment coupled to the analog block array, a second analog bus segment coupled to the analog block array, and a third analog bus segment coupled to the analog block array. The device also includes a first I/O pin selectively couplable to the first analog bus segment, a second I/O pin selectively couplable to the second analog bus segment, and a third I/O pin selectively couplable to the third analog bus segment. A first switch…
SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING
Granted: July 11, 2019
Application Number:
20190214995
In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements…
PROGRAMMABLE INPUT/OUTPUT CIRCUIT
Granted: July 11, 2019
Application Number:
20190214990
A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages…
METHOD FOR PROVIDING READ DATA FLOW CONTROL OR ERROR REPORTING USING A READ DATA STROBE
Granted: July 11, 2019
Application Number:
20190212920
A peripheral device includes a function block to provide data in response to a request from a host device, a data channel coupled with the function block to transmit the data from the function block to a host device as one or more packets, and output logic coupled with the data channel and configured to indicate validity of the data transmitted via the data channel by causing a signal to transition for each of the one or more packets of the data transmitted to the host device via the…
PRESSURE DETECTION AND MEASUREMENT WITH A FINGERPRINT SENSOR
Granted: July 4, 2019
Application Number:
20190205604
A circuit, system, and method for measuring or detecting pressure or force of a fingerprint on an array of electrodes is described. Pressure or force may be measured or detected using a processed image of the fingerprint, or by measurement of capacitance of deformed variable capacitors.
Uniformity correction method for low cost and non-rectangular touch sensor matrices
Granted: June 27, 2019
Application Number:
20190196653
Systems and methods access a correction value in a correction matrix. The correction matrix defines an active region of a touch array that includes plurality of unit cells. The correction value corresponds to a unit cell of the plurality of unit cells. Systems and methods modify a touch sense value of the unit cell using the correction value, based on the unit cell being partially within the active region. Systems and methods detect an object using the touch array, based on the modified…
Buried Trench Isolation in Integrated Circuits
Granted: June 27, 2019
Application Number:
20190198611
A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method…
SONOS Stack With Split Nitride Memory Layer
Granted: June 27, 2019
Application Number:
20190198329
A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and…
MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOF
Granted: June 27, 2019
Application Number:
20190198328
A memory device that has a first gate disposed adjacent to a second gate and a first dielectric structure disposed between the first and second gates. The first dielectric structure has at least four layers of oxide and nitride films arranged in an alternating layer, in which each of the at least four or more layers includes a width in an approximate range of 30 ? or less. The first dielectric structure further includes a top surface that is substantially un-etched.
NON-VOLATILE MEMORY DEVICE AND METHOD OF BLANK CHECK
Granted: June 27, 2019
Application Number:
20190198125
A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of…
NON-VOLATILE MEMORY ARRAY WITH MEMORY GATE LINE AND SOURCE LINE SCRAMBLING
Granted: June 27, 2019
Application Number:
20190198124
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with…
