METHOD AND APPARATUS FOR DATA TRANSMISSION VIA CAPACITANCE SENSING DEVICE
Granted: August 29, 2013
Application Number:
20130225072
Embodiments described herein provide methods, devices, and systems for a touch sensor, or capacitive sensing device, interact with external objects. One method utilizes a capacitive profile on the external object. Another method involves the use of a capacitive sensor array for wireless communication.
BALL GRID STRUCTURE
Granted: August 15, 2013
Application Number:
20130211776
An apparatus includes a contact grid array disposed on a substrate in a non-orthogonal row-column format with connection elements arranged in a hexagonal configuration. The contact grid array has an orientation based, at least in part, on an area available for the contact grid array on the substrate. A method to determine the orientation of the contact grid array includes identifying the area available for a contact grid array on a substrate and determining the orientation for the…
METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW
Granted: August 15, 2013
Application Number:
20130210209
Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in…
INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES
Granted: July 11, 2013
Application Number:
20130178031
An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping…
METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW
Granted: July 11, 2013
Application Number:
20130178030
An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel…
NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION
Granted: July 11, 2013
Application Number:
20130175604
An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a…
SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER
Granted: July 11, 2013
Application Number:
20130175600
Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer…
INLINE METHOD TO MONITOR ONO STACK QUALITY
Granted: July 11, 2013
Application Number:
20130175599
Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first…
OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
Granted: July 11, 2013
Application Number:
20130175504
An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric…
CAPACITOR POWER SOURCE TAMPER PROTECTION AND RELIABILITY TEST
Granted: July 4, 2013
Application Number:
20130170312
A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total…
HIGH VOLTAGE TOLERANT ROW DRIVER
Granted: July 4, 2013
Application Number:
20130170292
A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a second transistor and supplying a second voltage bias (VN1) and a second gate voltage (NG1) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP2) and a third gate voltage (PG2) to a…
CONTACT IDENTIFICATION AND TRACKING ON A CAPACITANCE SENSING ARRAY
Granted: July 4, 2013
Application Number:
20130169582
Active stylus operation when there is no physical connection between the stylus and the touch array requires communication and synchronization. It is possible to use the touchscreen stack-up itself to communicate synchronization signals or other information optically by outfitting the active stylus with an optical receiver and transmitting signals either with additional diodes or by modulating the display clock itself.
METHODS AND APPARATUS TO PERFORM A DETECTION OPERATION
Granted: July 4, 2013
Application Number:
20130169519
A method and apparatus determine a difference value, the determined difference value reflecting a difference between a plurality of presence values. In an embodiment, the method and apparatus perform an operation associated with the plurality of presence values, based on the determined difference value.
DEVICES AND METHODS HAVING CAPACITANCE SENSE STRUCTURE FORMED OVER HOUSING SURFACE
Granted: July 4, 2013
Application Number:
20130169294
A capacitance sensing system can include at least a first conductive pattern formed on a first surface of a housing of an electronic device; and a capacitance sensing circuit electrically connected to the first conductive pattern.
TOUCH SENSING
Granted: June 13, 2013
Application Number:
20130147732
A method and apparatus varying, by interval, a frequency of a drive signal applied to one electrode of each of a plurality of electrode pairs, select a frequency corresponding to the frequency of the drive signal, monitor changes in capacitance of each of the electrode pairs through receive signals at the selected frequency, from the other electrode of each of the plurality of electrode pairs; and determine a position of at least two objects, which are simultaneously on a touch device,…
UTILIZING USB RESOURCES
Granted: June 6, 2013
Application Number:
20130145056
At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.
INTERNAL DATA COMPARE FOR MEMORY VERIFICATION
Granted: June 6, 2013
Application Number:
20130141984
A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.
FLASH MEMORY DEVICES AND SYSTEMS
Granted: June 6, 2013
Application Number:
20130141978
Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective…
MEMORY CELL ARRAY LATCHUP PREVENTION
Granted: May 30, 2013
Application Number:
20130135954
A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within…
RE-ENUMERATION OF USB 3.0 COMPATIBLE DEVICES
Granted: May 23, 2013
Application Number:
20130132614
A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state.…
