Cypress Semiconductor Patent Grants

Microcontroller programmable system on a chip with programmable interconnect

Granted: September 19, 2017
Patent Number: 9766650
A programmable device includes reconfigurable analog circuitry, reconfigurable digital circuitry, a plurality of input/output (I/O) blocks, and a global mapping system. The global mapping system is configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

Position and usage based prioritization for capacitance sense interface

Granted: September 19, 2017
Patent Number: 9766738
A technique for improving capacitive sensing accuracy. Concurrent activations of multiple capacitance sensors within an array of capacitance sensors are sensed. One of the concurrent activations of the multiple capacitance sensors is accepted as a user activation. Remaining ones of the concurrent activations of the multiple capacitance sensors are rejected based on their physical location within the array of capacitance sensors relative to the one of the concurrent activations of the…

System for re-enumeration of USB 3.0 compatible peripheral devices

Granted: September 19, 2017
Patent Number: 9766901
Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.

Re-enumeration of USB 3.0 compatible devices

Granted: September 19, 2017
Patent Number: 9766902
A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state.…

Controlling the latchup effect

Granted: September 12, 2017
Patent Number: 9759764
A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

Touch sensing

Granted: September 12, 2017
Patent Number: 9760192
A method and apparatus varying, by interval, a frequency of a drive signal applied to one electrode of each of a plurality of electrode pairs, select a frequency corresponding to the frequency of the drive signal, monitor changes in capacitance of each of the electrode pairs through receive signals at the selected frequency, from the other electrode of each of the plurality of electrode pairs; and determine a position of at least two objects, which are simultaneously on a touch device,…

Mutual capacitance sensing array

Granted: September 5, 2017
Patent Number: 9753597
A method and apparatus for sensing a conductive object by a mutual capacitance sensing array is described according to an embodiment of the present invention. The mutual capacitance sensing array comprises one or more sensor elements. Each sensor element comprises an outer frame including a conductive material. A cavity is formed within the interior of the outer frame. In an example embodiment, the sensor elements include transmit (TX) sensor elements and receive (RX) sensor elements…

Acoustic processing unit interface for determining senone scores using a greater clock frequency than that corresponding to received audio

Granted: September 5, 2017
Patent Number: 9753890
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, a speech recognition system is provided. The system includes a processing unit configured to divide a received audio signal into consecutive frames having respective frame vectors, an acoustic processing unit (APU), a data bus that couples the processing unit and the APU. The APU includes a local, non-volatile memory that stores a plurality of senones, a memory buffer…

Detect and differentiate touches from different size conductive objects on a capacitive button

Granted: August 29, 2017
Patent Number: 9746507
Apparatuses and methods of distinguishing between a finger and a stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. The apparatus also includes a second circuit coupled to the first circuit. The second circuit is operable to detect whether the conductive object activates the first sense element, second sense element, or both, in view of the…

Providing a baseline capacitance for a capacitance sensing channel

Granted: August 29, 2017
Patent Number: 9746974
A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner may generate a baseline current using a baseline capacitor and may provide the baseline current to the channel input.

Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells

Granted: August 29, 2017
Patent Number: 9747987
Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.

SONOS stack with split nitride memory layer

Granted: August 29, 2017
Patent Number: 9748103
A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.

Stochastic signal density modulation for optical transducer control

Granted: August 29, 2017
Patent Number: 9750097
A controller for optical transducers uses stochastic signal density modulation to reduce electromagnetic interference.

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

Granted: August 22, 2017
Patent Number: 9741803
A charge trap memory device is provided. In one embodiment, the charge trap memory device includes a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region. A tunnel dielectric layer is disposed on the vertical channel, a multi-layer…

Multiple phase-shift photomask and semiconductor manufacturing method

Granted: August 15, 2017
Patent Number: 9733574
Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device…

Pressure detection system for touch-sense devices

Granted: August 15, 2017
Patent Number: 9733745
A touch-sense device includes an overlay, such as a rough overlay or a compliant overlay, on a sensing layer. Use of the overlay changes a response of the sensing layer so that a light press is more distinguishable from a strong press by sensing electronics. Distinguishing the light press from the strong press enables the sensing electronics to report additional information in response to a press. In one example, a sensor signal of the sensing layer attains a first magnitude for a light…

Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock

Granted: August 15, 2017
Patent Number: 9734877
A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate…

Ion implantation-assisted etch-back process for improving spacer shape and spacer width control

Granted: August 15, 2017
Patent Number: 9735289
Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a…

Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs

Granted: August 8, 2017
Patent Number: 9727123
Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a device comprises a Universal Serial Bus (USB) subsystem that is disposed in a monolithic integrated circuit (IC). The USB subsystem comprises a gate-driver circuit configured to selectively control an external N-channel power-FET or an external P-channel power-FET.

Method of depositing copper using physical vapor deposition

Granted: August 8, 2017
Patent Number: 9728414
The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.