Joint equalization, soft-demapping and phase error correction in wireless system with receive diversity
Granted: February 6, 2007
Patent Number:
7173990
A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among…
Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality
Granted: December 5, 2006
Patent Number:
7146134
An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value,…
Circuit package integrating passive radio frequency structure
Granted: November 21, 2006
Patent Number:
7138884
In general, the invention is directed to integration of passive radio frequency (RF) structures with at least one integrated circuit in a single integrated circuit (IC) package. An IC package in accordance with the invention may include, for example, a radio IC, a digital IC, a passive radio frequency balun as well as additional passive RF structures or ICs. Additionally, passive electronic components may further be incorporated in the IC package. For example, the IC package may include…
Enhanced frequency domain equalization in OFDM communication
Granted: August 29, 2006
Patent Number:
7099267
A technique for enhanced frequency domain equalization in an OFDM communication receiver enables derivation of a more accurate estimate of channel gain fluctuation by adding an additional frequency tone observation to the estimate. For example, the technique may involve estimation of an unknown, complex, channel-induced gain A based on observation of complex amplitude values for first and second preamble symbols transmitted in an OFDM frame, plus the complex amplitude value for a signal…
Multi-band antenna structure
Granted: August 8, 2006
Patent Number:
7088299
The invention provides a multi-band antenna structure for use in a wireless communication system. The antenna structure includes integrated inductive elements and capacitive elements that function as a tuned circuit to allow the antenna structure to operate in multiple frequency ranges. In particular, the capacitive elements electromagnetically couple to the inductive elements. The capacitive elements provide the inductive elements with parallel capacitance at a given set of frequencies,…
Transposable register file
Granted: May 30, 2006
Patent Number:
7054897
A register file structure efficiently handles matrix and image processing. The register file contains an array of data elements and has modes for accessing of multiple data values that are aligned horizontally or vertically in a data array and for accessing data having different widths for each data value. The different modes allow manipulation of a transposed array without requiring a transpose operation and permit fast horizontal or vertical filtering with parallel access and…
Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands
Granted: July 5, 2005
Patent Number:
6915322
A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a multiplication of double-width operands. In alternative embodiments, the adder operates in the same clock cycle as the multipliers or in a following clock cycle. Operand selection logic selects pairs of either single-width multiplicands or single-width partial multiplicands depending on for single or…
Co-prime division prescaler and frequency synthesizer
Granted: January 18, 2005
Patent Number:
6845139
A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes…
Two cycle FFT
Granted: September 23, 2003
Patent Number:
6625630
A digital signal processor (DSP) includes at least two multipliers, at least two three-input arithmetic logic units (ALU), at least two first-cycle registers, at least two second-cycle registers, and multiplexing apparatus. The digital signal processor is able to perform a Fast Fourier Transform (FFT) calculation in two consecutive processing cycles.
Compensation of frequency pulling in a time-division duplexing transceiver
Granted: July 22, 2003
Patent Number:
6597754
A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the…
Methods and apparatus for alteration of terminal counts of phase-locked loops
Granted: July 22, 2003
Patent Number:
6597246
A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.
Accumulation saturation by means of feedback
Granted: March 18, 2003
Patent Number:
6535900
A processor made up of a computation unit, an accumulator unit, a saturation determination unit and a saturation unit. The computation unit operates on one or more operands of W bits. The accumulator unit stores the output of the computation unit, in W bits. The saturation determination unit detects overflow in parallel with latching of the output of the computation unit. Overflow occurs when the operand latched by the accumulator represents a number having more than A significant bits,…
DSP for two clock cycle codebook search
Granted: September 17, 2002
Patent Number:
6452517
A device for performing a search for the optimum code vector in a codebook having N code vectors indexed by i has a controller which considers each ith code vector, and a processor which determines in two clock cycles whether said ith code vector is the current optimal code vector.
Dual access memory array
Granted: June 18, 2002
Patent Number:
6407961
A memory array includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N…
Frame synchronization in a digital communications system
Granted: August 14, 2001
Patent Number:
6275519
In a digital communication receiver, a system and method for recovering the timing of frames in the received signal. The receiver synchronizes an internal frame clock with a series of received data frames in the received data stream. One embodiment of a method for performing the frame synchronization proceeds by first recovering a symbol timing for data symbols in the received frames, then acquiring a frame timing by scanning the received data symbols for the SYNC field only during a…
Fast tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system
Granted: July 17, 2001
Patent Number:
6263013
In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment of the method, the receiver waits for detection of a SYNC field to confirm at least a coarse synchronization or the receiver's local PN sequence with the received PN sequence (in the received signal). The receiver then performs a fast tracking to finely synchronize the…
Two bit per cell ROM using a two phase current sense amplifier
Granted: July 10, 2001
Patent Number:
6259622
A read only memory (ROM) which is made up of an array and a current sensing circuit. The array is made up of a number of cells each cell being adapted for storing N bits. Each cell has an operative element which is of one of 2N sizes representative of a combination of N bits. The current sensing circuit is connected to the array and senses the size of the operative elements of the array. The current sensing circuit thus differentiates between the 2N sizes of the operative elements to…
Slow tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system
Granted: July 3, 2001
Patent Number:
6256335
In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the receiver performs a slow tracking to maintain the synchronization of the receiver's PN sequence with the received PN sequence. The slow tracking preferably includes one or more advancements or delays of the receiver's PN sequence if correlation measurements consistently…
Rapid acquisition of PN synchronization in a direct-sequence spread-spectrum digital communications system
Granted: July 3, 2001
Patent Number:
6256337
In a direct sequence spread spectrum communication system, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the communication system is a time-division duplexing (TDD) or a time-division multiple-access (TDMA) system. A receiver in the communication system uses a “sliding correlator” maximal-likelihood (ML) detection system to scan through a range of possible PN phases to…
Symbol-quality evaluation in a digital communications receiver
Granted: April 3, 2001
Patent Number:
6212246
In a digital communications receiver, a system and method for evaluating the quality of received symbols and for initializing and adjusting a symbol clock. The invention presents a symbol quality detector that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are members of a constellation with elements that have purely I or purely Q components. The symbol-quality detector comprises inputs that receive the I and Q components…
