Closed-grid bus architecture for wafer interconnect structure
Granted: September 11, 2003
Application Number:
20030169061
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first…
Method and system for detecting an arc condition
Granted: July 3, 2003
Application Number:
20030122568
A method and apparatus for detecting an arc condition in a semiconductor test system is disclosed. While probes in a semiconductor test system are being moved into or out of contact with a semiconductor wafer, the voltage level of power supplied to selected ones of the probes is monitored. If the voltage level of the power exceeds a level that could cause an arc between the probes and the semiconductor wafer while the wafer is being moved, an indication is generated that an arc condition…
Distributed interface for parallel testing of multiple devices using a single tester channel
Granted: July 3, 2003
Application Number:
20030126534
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values…
Inductive heating of microelectronic components
Granted: June 26, 2003
Application Number:
20030115749
A method for heat-treating a plurality of microelectronic structures attached to a non-metallic substrate is disclosed. Each of the plurality of microelectronic structures is comprised of a metallic material, and ones of the plurality of metallic microelectronic structures are insulated from other ones of the plurality of microelectronic structures. An application of the method is for heat-treatment of resilient microstructures. The method comprises the steps of: (a) placing the…
Microelectronic spring contact repair
Granted: June 19, 2003
Application Number:
20030113990
A method for replacing a microelectronic spring contact bonded to a terminal of a substrate is disclosed. The method comprises removing the microelectronic spring contact from the terminal, such as by cutting the microelectronic spring contact in two adjacent to the terminal. Then, a bonding material, such as a solder paste, is applied to the terminal and a replacement spring contact is positioned on the bonding material. The bonding material is then cured to fix the replacement spring…
Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes
Granted: June 19, 2003
Application Number:
20030115568
A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and…
Wafer-level burn-in and test
Granted: June 12, 2003
Application Number:
20030107394
Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly…
Forming tool for forming a contoured microelectronic spring mold
Granted: May 29, 2003
Application Number:
20030099737
A forming tool with one or more embossing tooth, and preferably, a plurality of such embossing teeth, arranged on a substantially planar substrate, is disclosed. Each embossing tooth is configured for forming a sacrificial layer to provide a contoured surface for forming a microelectronic spring structure. Each embossing tooth has a protruding area corresponding to a base of a microelectronic spring, and a sloped portion corresponding to a beam contour of a microelectronic spring.…
High frequency printed circuit board via
Granted: May 1, 2003
Application Number:
20030080835
A printed circuit board (PCB) via, providing a conductor extending vertically between microstrip or stripline conductors formed on separate layers of a PCB, includes a conductive pad surrounding the conductor and embedded within the PCB between those PCB layers. The pad's shunt capacitance and the magnitudes of capacitances of other portions of the via are sized relative to the conductor's inherent inductance to optimize frequency response characteristics of the via.
Fan out of interconnect elements attached to semiconductor wafer
Granted: May 1, 2003
Application Number:
20030082890
An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.
Sockets for "springed" semiconductor devices
Granted: April 10, 2003
Application Number:
20030067080
Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.
Process and apparatus for finding pahts through a routing space
Granted: April 10, 2003
Application Number:
20030070153
An initial graph of nodes is created within a routing space, and the number and locations of the nodes in the graph are adjusted. Links are created between nodes of the graph, and traces between specified nodes are created through the linked graph.
Integrated circuit tester with high bandwidth probe assembly
Granted: April 10, 2003
Application Number:
20030067316
Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.
Method for manufacturing raised electrical contact pattern of controlled geometry
Granted: April 3, 2003
Application Number:
20030062398
Spring contact elements are attached to terminals of an electronic component, which may be a semiconductor die. The spring contact elements may comprise a flexible precursor element. The precursor element may be over coated with a resilient material. The spring contact elements may be elongate and attached to the terminals at one end. The other end of the spring contacts may be spaced away from the electronic component.
Segmented contactor
Granted: March 27, 2003
Application Number:
20030057975
A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into…
Method and system for designing a probe card
Granted: March 20, 2003
Application Number:
20030055736
A method and system for designing a probe card from data provided by prospective customers via the Internet is provided. Design specifications are entered into the system by prospective customers and compiled into a database. The collective feasibility of each set of design specifications is determined by an automated computer system and communicated to the prospective customer. If feasible, additional software enables prospective customers to create verification packages according to…
Method of assembling and testing an electronics module
Granted: March 13, 2003
Application Number:
20030049873
An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested…
Microelectronic contact structures, and methods of making same
Granted: March 13, 2003
Application Number:
20030049951
Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a “post” component, a “beam” component, and a “tip” component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be fabricated on a sacrificial substrate, joined to…
Process and apparatus for adjusting traces
Granted: February 27, 2003
Application Number:
20030038850
Traces routed through a computer depiction of a routing area of an electronics system comprise a plurality of connected nodes. Forces are assigned to the nodes, and the nodes are moved in accordance with the forces. The forces may be based on such things as the proximity of the nodes to each other and to obstacles in the routing area. This tends to smooth, straighten and/or shorten the traces, and may also tend to correct design rule violations.
Method of manufacturing a probe card
Granted: February 6, 2003
Application Number:
20030025172
A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the…
