COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS
Granted: July 22, 2021
Application Number:
20210225436
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS
Granted: July 22, 2021
Application Number:
20210225437
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATIONAL MEMORY CELLS
Granted: July 15, 2021
Application Number:
20210216246
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
ORTHOGONAL DATA TRANSPOSITION SYSTEM AND METHOD DURING DATA TRANSFERS TO/FROM A PROCESSING ARRAY
Granted: June 10, 2021
Application Number:
20210173647
A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.
PROCESSING ARRAY DEVICE THAT PERFORMS ONE CYCLE FULL ADDER OPERATION AND BIT LINE READ/WRITE LOGIC FEATURES
Granted: January 28, 2021
Application Number:
20210027815
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
WRITE DATA PROCESSING METHODS ASSOCIATED WITH COMPUTATIONAL MEMORY CELLS
Granted: January 28, 2021
Application Number:
20210027834
A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
SYSTEMS AND METHODS INVOLVING PSEUDO COMPLEMENTARY OUTPUT BUFFER CIRCUITRY/SCHEMES, POWER NOISE REDUCTION AND/OR OTHER FEATURES
Granted: March 2, 2017
Application Number:
20170063372
A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may b e coupled to an output of the second inverter on a first terminal and a ground on a second terminal,…
Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs
Granted: October 9, 2014
Application Number:
20140304463
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide…
SYSTEMS AND METHODS OF PIPELINED OUTPUT LATCHING INVOLVING SYNCHRONOUS MEMORY ARRAYS
Granted: September 25, 2014
Application Number:
20140286083
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the…
SYSTEMS AND METHODS INVOLVING DATA BUS INVERSION MEMORY CIRCUITRY, CONFIGURATION AND/OR OPERATION
Granted: September 25, 2014
Application Number:
20140289440
Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides…
SYSTEMS AND METHODS INVOLVING DATA BUS INVERSION MEMORY CIRCUITRY, CONFIGURATION AND/OR OPERATION INCLUDING DATA SIGNALS GROUPED INTO 10 BITS AND/OR OTHER FEATURES
Granted: September 25, 2014
Application Number:
20140289460
Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI…
LASER ADJUSTABLE DEPTH MARK SYSTEM AND METHOD
Granted: July 16, 2009
Application Number:
20090179015
A system and method for adjustable laser mark depth is provided. In one embodiment, the system is used in Nd—YAG laser marker for wafer processing in the semiconductor industry, with smart control of the mark depth and expanded work range between the deep mark and the light mark.
SYSTEM AND METHOD FOR REFRESHING A DRAM DEVICE
Granted: February 7, 2008
Application Number:
20080031069
The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the…
