Digital signal generator
Granted: January 28, 2014
Patent Number:
8638174
The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and…
Systems, devices, and methods for providing backup power to a load
Granted: January 28, 2014
Patent Number:
8638010
Systems, devices, and methods for providing backup power to a load are disclosed. A power converter may comprise a capacitor array comprising a plurality of capacitors and configured to store a charge from an input during a charge mode of operation and provide a charge to an output during a discharge mode of operation. Further, the power converter may comprise a controller configured to selectively couple the capacitor array to the input during a portion of the charge mode of operation…
Microelectromechanical resonators with thermally-actuated frequency tuning beams
Granted: January 21, 2014
Patent Number:
8633635
A microelectromechanical resonator includes a resonator body anchored to a substrate by at least a pair of tethers that suspend the resonator body opposite an underlying opening in the substrate. A first thermally-actuated tuning beam is provided, which is mechanically coupled to a first portion of the resonator body that is spaced apart from the pair of tethers. The first thermally-actuated tuning beam is configured to induce a mechanical stress in the resonator body by establishing a…
Method to support flexible data transport on serial protocols
Granted: January 7, 2014
Patent Number:
8625621
A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the…
Apparatuses and methods for reducing power in driving display panels
Granted: January 7, 2014
Patent Number:
8624818
Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is…
Systems and methods for adjusting ultra-small metal-oxide-metal capacitors
Granted: December 24, 2013
Patent Number:
8614472
An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.
Methods and apparatuses for flexible and high performance digital signal processing
Granted: December 17, 2013
Patent Number:
8612503
A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor…
Tree structured supply and bias distribution layout
Granted: December 17, 2013
Patent Number:
8610612
Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.
Microelectromechanical resonators having resistive heating elements therein configured to provide frequency tuning through convective heating of resonator bodies
Granted: December 17, 2013
Patent Number:
8610336
A microelectromechanical resonator includes a resonator body, which is encapsulated within a sealed cavity extending between first and second substrates that are bonded together. The resonator body is anchored to the first substrate by at least a pair of tethers that suspend the resonator body opposite an underlying recess in the first substrate. A resistive heating element is provided, which is configured to indirectly heat the resonator body through convective heating of the cavity.…
Matched feedback amplifier with improved linearity
Granted: December 10, 2013
Patent Number:
8604879
An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in…
MEMS-based frequency synthesizers having variable bandwidth temperature compensation
Granted: December 10, 2013
Patent Number:
8604848
A frequency synthesizer includes a frequency generator configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent code. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent code in response to the temperature…
MEMS-based frequency synthesizers with enhanced temperature compensation
Granted: November 5, 2013
Patent Number:
8575981
A frequency synthesizer is configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent frequency adjusting control signal. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent frequency adjusting control signal…
Microelectromechanical resonators with passive frequency tuning using built-in piezoelectric-based varactors
Granted: November 5, 2013
Patent Number:
8575819
Microelectromechanical resonators include a resonator body with a built-in piezoelectric-based varactor diode. This built-in varactor diode supports passive frequency tuning by enabling low-power manipulation of the stiffness of a piezoelectric layer, in response to controlling charge build-up therein at resonance. A resonator may include a composite stack of a bottom electrode, a piezoelectric layer on the bottom electrode and at least one top electrode on the piezoelectric layer. The…
Methods and apparatuses for cordic processing
Granted: October 29, 2013
Patent Number:
8572151
A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The…
Method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer and continuous transfer modes
Granted: October 29, 2013
Patent Number:
8571050
A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can quickly optimize network traffic with multiple VCs and mixed RT/CT modes.
Fractional-N dividers having divider modulation circuits therein with segmented accumulators
Granted: October 15, 2013
Patent Number:
8559587
Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider.…
Frequency synthesizers with dynamic calibration intervals
Granted: October 8, 2013
Patent Number:
8552804
An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the…
High speed chip screening method using delay locked loop
Granted: October 1, 2013
Patent Number:
8548773
A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output…
Reconfigurable divider circuits with hybrid structure
Granted: September 24, 2013
Patent Number:
8542040
An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further…
Data converter current sources using thin-oxide core devices
Granted: September 17, 2013
Patent Number:
8537040
Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.
