Contact architecture for capacitance reduction and satisfactory contact resistance
Granted: February 11, 2025
Patent Number:
12224326
Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric…
Dual metal silicide structures for advanced integrated circuit structure fabrication
Granted: February 11, 2025
Patent Number:
12225740
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is…
Channel access enhancements for ultra-reliable low-latency communication (URLLC) in unlicensed spectrum
Granted: February 11, 2025
Patent Number:
12225582
Embodiments of a user equipment (UE) configurable for unlicensed band operation in a 5G NR system (5GS), when operating in semi-static channel access mode, for a UE-initiated channel-occupancy time (COT), is configured to transmit an uplink (UL) transmission burst, as an initiating device, starting at a beginning of fixed frame period (FFP) and ending at a symbol before an idle period of the FFP after a successful clear-channel assessment (CCA).
Enhanced high efficiency frames for wireless communications
Granted: February 11, 2025
Patent Number:
12225514
This disclosure describes systems, methods, and devices related to using enhanced high efficiency (HE) frames. A device may determine a high efficiency signal-B (HE-SIG-B) field for a high efficiency (HE) frame, the HE-SIG-B field comprising a common information field and a user information field. The device may determine a data portion of the HE frame, wherein the data portion includes one or more resource units (RUs) with a size equal to a number of tones. The device may determine a…
Methods and apparatus to mitigate coexistence interference in a wireless network
Granted: February 11, 2025
Patent Number:
12225391
Methods and apparatus to mitigate coexistence interference in a wireless network are disclosed. An example apparatus includes a station component interface to receive an expected transmission power from an access point; an index processor to determine a set of preferred resource unit (RU) indexes from a set of available RU indexes for at least one of (A) uplink transmission to the access point based on a comparison of allowable transmission power and the expected transmission power or…
Data offload and time synchronization for ubiquitous visual computing witness
Granted: February 11, 2025
Patent Number:
12225131
In one embodiment, a road side unit (RSU) establishes a data offload session with a vehicle in the vicinity of the RSU based on a session establishment request sent by the vehicle, and stores data received from the vehicle during the data offload session in its memory. The RSU generates storage record information (including identifying information for the RSU) for the stored data, and transmits the storage record information to the vehicle.
Selective congestion notification by a network interface device
Granted: February 11, 2025
Patent Number:
12224940
Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message…
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
Granted: February 11, 2025
Patent Number:
12224350
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second…
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls
Granted: February 11, 2025
Patent Number:
12224349
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the…
PGaN enhancement mode HEMTs with dopant diffusion spacer
Granted: February 11, 2025
Patent Number:
12224337
III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG…
Capacitors with built-in electric fields
Granted: February 11, 2025
Patent Number:
12224309
Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.
Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
Granted: February 11, 2025
Patent Number:
12224264
Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first…
Mixed hybrid bonding structures and methods of forming the same
Granted: February 11, 2025
Patent Number:
12224261
Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive…
Magnetic inductor device and method
Granted: February 11, 2025
Patent Number:
12224253
Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical…
Magnetic core inductors in interposer
Granted: February 11, 2025
Patent Number:
12224252
Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.
Embedded die architecture and method of making
Granted: February 11, 2025
Patent Number:
12224245
Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate.…
Internal node jumper for memory bit cells
Granted: February 11, 2025
Patent Number:
12224239
Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate…
Dry film lamination with dynamic feedback control
Granted: February 4, 2025
Patent Number:
12214579
The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations…
Apparatuses and methods for inspecting embedded features
Granted: February 4, 2025
Patent Number:
12216301
An apparatus includes a light source configured to emit light to a translucent material and an embedded feature disposed in the translucent material, a first linear polarizer configured to linearly polarize the emitted light, based on a first orientation of an optical axis of the first linear polarizer, and a second linear polarizer configured to filter the light that is reflected from the translucent material, from the light that is reflected from the embedded feature and the…
Contactless optical probing of edge-coupled photonic ICs
Granted: February 4, 2025
Patent Number:
12216158
Systems and methods for testing a photonic IC (PIC) with an optical probe having an out-of-plane edge coupler to convey test signals between the out-of-plane probe and an edge coupled photonic waveguide within a plane of the PIC. To accommodate dimensions of the optical probe, a test trench may be fabricated in the PIC near an edge coupler of the waveguide. The optical probe may be displaced along one or more axes relative to a prober to position a free end of the prober within the test…
