LIGHT SENSORS WITH INFRARED SUPPRESSION
Granted: October 7, 2010
Application Number:
20100252871
Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.
SYSTEM AND METHOD FOR PHASE DROPPING AND ADDING
Granted: September 30, 2010
Application Number:
20100244799
A multi-phase voltage regulator comprisies a plurality of current supplying stages, each current supplying stage configured to supply a local output current equaling at least a portion of a load current output from the multi-phase voltage regulator; and a plurality of control circuits, each control circuit coupled to a respective one of the plurality of current supplying stages, wherein each control circuit calculates a control signal based, at least in part, on a sampled current…
UN-BUFFERED SEGMENTED R-DAC WITH SWITCH CURRENT REDUCTION
Granted: September 30, 2010
Application Number:
20100245145
An resistor string digital-to-analog converter (DAC) that includes elements to compensate for resistor ladder loading, and/or to provide compensation for loading such as via switch current cancellation. The approach reduces output voltage sensitivity to switch resistances while also reducing INL and DNL errors. Additional resistor loops are optionally disposed at the top and bottom of one or more further segments to provide Nth order resistive current cancellation.
BI-DIRECTIONAL BUFFER FOR OPEN-DRAIN OR OPEN-COLLECTOR BUS
Granted: August 19, 2010
Application Number:
20100207661
Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node.…
DYNAMIC PHASE TIMING CONTROL FOR MULTIPLE REGULATORS OR PHASES
Granted: August 12, 2010
Application Number:
20100201405
A drive control circuit generates switching drive signals for a single phase of a multiphase voltage regulator. A driver circuitry generates the switching drive signals for the voltage regulator responsive to a clock signal. A clock circuitry generates the clock signal responsive to a monitored external clock signal. A phase number detector determines a number of active phases in the multiphase voltage regulator in real time responsive to an indicator on a phase number input monitored by…
CONNECTION SYSTEMS AND METHODS FOR SOLAR CELLS
Granted: July 29, 2010
Application Number:
20100191383
Exemplary embodiments provide an array of solar power generation devices, and method for forming the array. Each solar power generation device can be defined as a cell, a group of cells, a panel subarray, a panel from an array of panels, etc. The solar power generation device can include a controller which can address and control each solar power generation device individually. A test method and fixture is also described, which can be used to program the controller such that incorrect…
DYNAMICALLY CONFIGURABLE MULTIPLE WAVELENGTH PHOTODETECTOR ARRAY FOR OPTICAL STORAGE APPLICATIONS
Granted: July 15, 2010
Application Number:
20100177625
A photodetector integrated circuit (PDIC) capable of being used with at least two different types of optical discs includes a photodetector (PD) array and a switch matrix. The PD array includes a center channel PD and a side channel PD electrically isolated from the center channel PD. The switch matrix, which includes a plurality of inputs and a plurality of outputs, can be selectively configured in a plurality of different switch configurations. The side channel PD includes a plurality…
N-BIT ADC READER
Granted: July 8, 2010
Application Number:
20100171645
An integrated circuit including a single input pin for determining a value associated with a resistor divider. The circuit includes first circuitry for determining a resistor ratio of the resistor divider through the single input pin. A first register stores a first group of bits representing the resistor ratio. The first group of bits comprises the least significant bits of the value. Second circuitry determines an equivalent resistance of the resistor divider through the single input…
FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS
Granted: June 17, 2010
Application Number:
20100149879
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of…
ACTIVE PULSE POSITIONING MODULATOR
Granted: June 10, 2010
Application Number:
20100141225
An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal…
FAULT TOLERANT REDUNDANT CLOCK CIRCUIT
Granted: May 27, 2010
Application Number:
20100127679
A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal.…
BASE FOR A NPN BIPOLAR TRANSISTOR
Granted: May 27, 2010
Application Number:
20100129975
An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.
CURRENT SENSE CASCODE AMPLIFIER
Granted: May 27, 2010
Application Number:
20100127684
A current sense amplifier sensing current through a main switch of a converter. The amplifier includes first and second switch devices, an amplifier control circuit, a bias circuit, a current generator circuit, and a sense circuit. The main switch is coupled to an input, phase and control nodes. The first and second switch devices are smaller matching versions of the main switch and are both coupled to the main switch and form first and second nodes. The bias circuit is coupled between…
PWM VOLTAGE CONVERTER WITH TRANSIENT AND PERMANENT FAULT IMMUNITY THROUGH REDUNDANCY AND FEEDBACK ADJUSTMENT
Granted: May 27, 2010
Application Number:
20100127680
A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding…
INTEGRATED PROCESS FOR THIN FILM RESISTORS WITH SILICIDES
Granted: May 13, 2010
Application Number:
20100117198
The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute…
Cable Gateway Using A Charge-Domain Pipeline Analog to Digital Converter
Granted: May 13, 2010
Application Number:
20100117883
A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages.
TUNABLE VOLTAGE ISOLATION GROUND TO GROUND ESD CLAMP
Granted: May 6, 2010
Application Number:
20100109631
A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.
CABLE EQUALIZATION LOCKING
Granted: May 6, 2010
Application Number:
20100110288
Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller…
SYSTEMS AND METHODS FOR CABLE EQUALIZATION
Granted: May 6, 2010
Application Number:
20100110299
Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller…
AUXILIARY TURN-ON MECHANISMS FOR REDUCING CONDUCTION LOSS IN BODY-DIODE OF LOW SIDE MOSFET OF COUPLED-INDUCTOR DC-DC CONVERTER
Granted: April 29, 2010
Application Number:
20100102791
An embodiment of a power-supply controller includes first and second circuits. The first circuit is operable to cause a first current to flow through a first phase of a power supply. And the second circuit is operable to cause the second phase of the power supply to operate in a reduced-power-dissipation mode for at least a portion of a time period during which a second current magnetically induced by the first current flows through the second phase.
