Exposed solderable heat spreader for flipchip packages
Granted: March 10, 2020
Patent Number:
10586757
A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation…
I2C device extender for inter-board communication over a single-channel bidirectional link
Granted: March 10, 2020
Patent Number:
10585834
A first circuit board includes a master device and slave devices communicating with each other via a local first I2C bus. To allow I2C networks to communicate with each other over long distances, such as up to 1200 meters, a first interface device converts the I2C data signals to encoded differential data over a twisted wire pair. A second interface device on a remote circuit board converts the differential data to data and clock signals on its local second I2C bus coupled to other slave…
Reference signal correction circuit
Granted: February 11, 2020
Patent Number:
10557894
In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference…
Hybrid inverting PWM power converters
Granted: January 28, 2020
Patent Number:
10547241
A hybrid power converter includes a primary switching circuit, an LC circuit, and a secondary switching circuit. The primary switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at a connecting node between two switching transistors. The LC circuit may be coupled via the to the secondary switching circuits to the connecting node of the primary switching circuit. The LC…
Fault-tolerant power network
Granted: January 28, 2020
Patent Number:
10547206
One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first…
Differential controller with regulators
Granted: January 21, 2020
Patent Number:
10541608
Various examples described herein are directed to a differential controller including a first regulator and a second regulator. The first regulator receives a first regulator control signal and generates a first regulator output signal. The second regulator receives a second regulator control signal and generates a second regulator output signal. A load is electrically coupled between a first regulator output and a second regulator output. The load current and voltage are based on a…
Monitoring of channel stability and interference in wireless networks
Granted: January 14, 2020
Patent Number:
10536861
The stability of a channel in a wireless network is evaluated at a node. Upon transmitting a packet from the node on a network channel, a first counter associated with the channel is incremented. Upon receiving an acknowledgment packet responsive to the transmitted packet, a second counter associated with the channel is incremented. A stability metric for the channel is computed based on values stored in the first and second counters. Additionally, interference on a channel of the…
Current mode switching regulator and operating method with offset circuitry to emulate a transient load step response
Granted: January 14, 2020
Patent Number:
10534384
A current mode switching regulator circuit and operating method includes a variable duty cycle power switch controller, a voltage feedback loop that provides a feedback signal based on the output voltage, a current feedback loop that provides a current sense signal based on the output current, and an offset circuit having an external signal input and coupled to the current feedback loop. The power switch controller controls the switching regulator circuit to generate an output voltage…
Coordinated event sequencing
Granted: January 7, 2020
Patent Number:
10528501
Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence…
Power interface system for reducing power variations in an output power of switching regulators
Granted: December 17, 2019
Patent Number:
10511234
A power interface system for reducing power variations includes multiple control circuits configured to control a plurality of switching regulators operating at different frequencies to provide a shared output power to a load. Each control circuit receives a power variation signal resulting from a power variation in the shared output power of the plurality of switching regulators, separates a respective frequency component from multiple frequency components of the power variation signal,…
Stacked circuit package with molded base having laser drilled openings for upper package
Granted: December 3, 2019
Patent Number:
10497635
A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder…
Multi-chip timing alignment to a common reference signal
Granted: December 3, 2019
Patent Number:
10496127
The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation…
Selective disabling of communication services provided by a wireless network
Granted: November 5, 2019
Patent Number:
10469339
A network manager of a wireless mesh network is configured to selectively enable or disable communication services provided between devices over the network. The selective enabling or disabling of services may be based on the monitoring and enforcement of license terms set according to license information embedded within the wireless network node(s) or access point(s) of the network. In operation, the network manager retrieves the license information from the node(s) and/or access…
Balancing techniques and circuits for charge pumps
Granted: November 5, 2019
Patent Number:
10468978
Methods and systems of pre-balancing a switched capacitor converter are provided. A first comparator includes a positive input configured to receive a voltage across an output capacitor and a negative input configured to receive a first hysteresis voltage. A second comparator includes a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter and a negative input configured to receive a second hysteresis voltage. A first current source…
High dynamic range analog-to-digital converter
Granted: October 15, 2019
Patent Number:
10447291
Techniques to provide automatic-gain ranging for high dynamic range by including a separate S/H capacitor, segmenting the S/H capacitor into a plurality of capacitors, and determining the number of segments to use for a sample. In this manner, the size of the S/H capacitor can be changed (by adjusting the number of capacitors), which can change the amount of input voltage that produces an amount of charge. Using these techniques, the full-scale input range for a sample of the analog…
Driving charge pump circuits
Granted: October 15, 2019
Patent Number:
10447152
A method and system of driving a switched capacitor converter having a plurality of switches. A first driver coupled to a first switch is powered by providing a first reference voltage level VCC to a first supply and a GND reference to a second supply node of the first driver. A second driver coupled to a second switch is powered by providing a unidirectional path between the first supply node of a first driver and the first supply node of the second driver and by keeping OFF the second…
Communications system using hybrid common mode choke and kelvin sensing of voltage
Granted: October 15, 2019
Patent Number:
10444823
In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common…
Termination for wire pair carrying DC and differential signals
Granted: September 24, 2019
Patent Number:
10425237
A PHY is coupled across a primary winding of an isolation transformer for differential data transmission and reception between PHYs and for DC isolation. Positive and negative low impedance terminals of a DC power supply are coupled to first and second secondary windings of the transformer as split center taps of the transformer. Respective ends of the wires in the wire pair are coupled to the other ends of the secondary windings. Therefore, the power supply conducts DC current through…
Inrush control with multiple switches
Granted: September 17, 2019
Patent Number:
10418805
A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is…
Common mode noise attenuation techniques for twisted wire pair
Granted: September 3, 2019
Patent Number:
10404502
Various techniques are described to terminate a differential wire pair using combinations of CMCs, transformers, autotransformers, differential mode chokes (DMCs), and AC-coupling capacitors. The techniques improve the AC common mode insertion loss without attenuating the differential data signals, while easing the requirements of the CMC. In one example, an autotransformer, having a first winding, a second winding, and a center tap, is connected across a PHY, where the center tap…
