DATA STORAGE SYSTEM WITH CACHING USING APPLICATION FIELD TO CARRY DATA BLOCK PROTECTION INFORMATION
Granted: October 22, 2015
Application Number:
20150301956
In a data storage system in which a host system transfers data to a data storage controller having cache memory, the data storage controller can use a designated field of each of several cache data blocks, such as an application (APP) field, to contain protection information from fields of a host data block, such as the guard (GRD) and reference (REF) fields as well as the APP field.
FLASH-BASED DATA STORAGE WITH DUAL MAP-BASED SERIALIZATION
Granted: October 22, 2015
Application Number:
20150301934
A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability.
ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING
Granted: October 15, 2015
Application Number:
20150294739
A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that…
SOFT READ HANDLING OF READ NOISE
Granted: October 15, 2015
Application Number:
20150293808
Aspects of the disclosure pertain to methods and systems that are configured to handle excessive read noise in soft read systems. In an implementation, a method includes determining a number of unexpected patterns of a soft read of a memory cell after a soft decoding failure. The method also includes determining whether the number of unexpected patterns is greater than a threshold number of unexpected patterns. When it is determined that the number of unexpected patterns is greater than…
System, Method and Computer-Readable Medium for Dynamically Configuring an Operational Mode in a Storage Controller
Granted: October 8, 2015
Application Number:
20150286438
A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold…
BAD MEMORY UNIT DETECTION IN A SOLID STATE DRIVE
Granted: October 8, 2015
Application Number:
20150287478
An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is…
DEVICE ABSTRACTED ZONE MANAGEMENT OF SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE TOPOLOGIES
Granted: October 8, 2015
Application Number:
20150286604
Systems and methods provide zone management for devices in a Serial Attached Small Computer System Interface (SAS) topology. In one embodiment, a zone management device stores a zone map that identifies an initial zone of a device in the topology. The management device detects changes in the topology, and identifies a current zone of the device subsequent to the change in the topology. The management device compares the zone map for the device to the current zone to identify a change in…
ARBITRATION MONITORING FOR SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE SYSTEMS DURING DISCOVERY
Granted: October 8, 2015
Application Number:
20150286600
Methods and structure for detecting that arbitration is delaying discovery. One embodiment is a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes multiple SAS ports, a port monitor, and a controller. The port monitor is able to track physical link events during arbitration for at least one of the ports while discovery is in progress at the expander, and to detect based on the physical link events that arbitration is delaying discovery. The…
ERROR CORRECTION CODE (ECC) SELECTION IN NAND FLASH CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES
Granted: October 8, 2015
Application Number:
20150286528
An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined…
Systems and Methods for Differential Message Scaling in a Decoding Process
Granted: October 8, 2015
Application Number:
20150286523
Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit.
READ POLICY FOR SYSTEM DATA OF SOLID STATE DRIVES
Granted: October 8, 2015
Application Number:
20150286421
An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.
Systems and Methods for Skew Tolerant Multi-Head Data Processing
Granted: October 1, 2015
Application Number:
20150279415
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing skew tolerant processing of data derived from multiple read heads.
Locking a Disk-Locked Clock Using Timestamps of Successive Servo Address Marks in a Spiral Servo Track
Granted: October 1, 2015
Application Number:
20150279398
Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from…
Memory Sense Amplifier And Column Pre-Charger
Granted: September 24, 2015
Application Number:
20150269990
A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.
SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE TOTAL POWER WITHIN A CIRCUIT DESIGN
Granted: September 24, 2015
Application Number:
20150269304
A system is described that analyzes timing of a design and conditionally replaces values of a cell to lower total power within circuit paths having a positive timing margin. The system includes a computing device that includes a memory for storing modules and a processor that is operable to execute the modules. The modules cause the processor to conditionally replace a first semiconductor characteristic with a second semiconductor characteristic associated with a cell in a path of a…
System and Method for Elastic Despreader Memory Management
Granted: September 24, 2015
Application Number:
20150269097
The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer…
Multiple Core Execution Trace Buffer
Granted: September 24, 2015
Application Number:
20150269054
A data processing system includes a number of processor cores each having a trace interface with an address signal carrying program addresses being executed, a processor core identification circuit connected to the trace interfaces and operable to replace a portion of some of the program addresses with a processor core identification that identifies which of the processor cores provided the program addresses, and an execution trace buffer operable to store the program addresses…
WRITE REDIRECTION IN REDUNDANT ARRAY OF INDEPENDENT DISKS SYSTEMS
Granted: September 24, 2015
Application Number:
20150269025
Methods and structure for redirecting writes in Redundant Array of Independent Disks (RAID) systems are provided. One exemplary embodiment is a RAID controller that includes a memory and a control unit. The memory is able to store mapping information that correlates Logical Block Addresses of a RAID volume with physical addresses of storage devices. The control unit is able to generate a request to write volume data to at least one of the physical addresses, to determine that a storage…
READ DISTURB HANDLING IN NAND FLASH
Granted: September 24, 2015
Application Number:
20150268871
An apparatus having a processor and an interface to a nonvolatile memory having a plurality of blocks is disclosed. The processor is configured to (i) monitor a number of reads since a respective erase in at least one of the blocks in the nonvolatile memory, (ii) move a page from a first block to a second block in response to the number of reads exceeding a first threshold where the first block is partially programmed and (iii) move the page from the first block to the second block in…
LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY
Granted: September 17, 2015
Application Number:
20150262667
An apparatus includes a hit bitline driver circuit and an equalization control circuit. The hit bitline driver circuit may be configured to drive a pair of hit bitlines responsive to a search bit. The equalization control circuit may be configured to transfer charge from one hit bitline of the pair to the other hit bitline of the pair in response to the search bit changing state.
