IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
Granted: January 19, 2012
Application Number:
20120017190
An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3)…
LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING
Granted: January 19, 2012
Application Number:
20120017132
In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual…
METHOD OF CHARACTERIZING REGULAR ELECTRONIC CIRCUITS
Granted: January 12, 2012
Application Number:
20120011483
A methods of characterizing a regular electronic circuit and using a parameterized model of an electronic circuit to create a model for another electronic circuit. In one embodiment, the method of characterizing includes: (1) characterizing fewer than all sub-circuits associated with input and output pins of the circuit to yield data regarding the sub-circuits, (2) generating a data file containing the data, the data file constituting an expandable parameterized model of the circuit.
FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT
Granted: January 12, 2012
Application Number:
20120008450
A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b)…
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED TIMING-REALIZABLE CLOCK-INSERTION DELAYS AND INTEGRATED CIRCUIT DESIGN TOOLS
Granted: January 12, 2012
Application Number:
20120011484
A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the…
ON-LINE DISCOVERY AND FILTERING OF TRAPPING SETS
Granted: January 5, 2012
Application Number:
20120005552
A communication system (e.g., a hard drive) having a random-access memory (RAM) for storing trapping-set (TS) information that the communication system generates on-line during a special operating mode, in which low-density parity-check (LDPC)-encoded test codewords are written to a storage medium and then read and decoded to discover trapping sets that appear in candidate codewords produced by an LDPC decoder during decoding iterations. The discovered trapping sets are filtered to…
MANAGING PROTECTED AND UNPROTECTED DATA SIMULTANEOUSLY
Granted: January 5, 2012
Application Number:
20120005669
A first virtual device is created including every logically addressable unit of a data storage server that utilizes data protection. A second virtual device is created including no logically addressable unit of the data storage server that utilizes data protection. Data transfers are disabled within all command phases of the first virtual device.
BREAKING TRAPPING SETS USING TARGETED BIT ADJUSTMENT
Granted: January 5, 2012
Application Number:
20120005551
In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if…
Power Supply Noise Injection
Granted: December 29, 2011
Application Number:
20110316504
A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator.
CONDITIONAL SKIP-LAYER DECODING
Granted: December 29, 2011
Application Number:
20110320902
In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a…
Delay-Cell Footprint-Compatible Buffers
Granted: December 29, 2011
Application Number:
20110320997
A method for creating a design for an integrated circuit, by developing a set of delay cells where each of the cells in the set has a different delay time from the other cells in the set, and where each of the cells in the set has the same surface area, has the same pin-outs, has the same drive strength, and has the same input capacitance, where an originally-used cell in the set can be swapped out for a different replacement cell in the set without any impact on the design of the…
Multi-Port Memory Using Single-Port Memory Cells
Granted: December 22, 2011
Application Number:
20110310691
A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array.…
Turbo-Equalization Methods For Iterative Decoders
Granted: December 22, 2011
Application Number:
20110311002
Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i?1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved…
ELECTROCHEMICAL CELL SYSTEM AND APPARATUS TO PROVIDE ENERGY TO A PORTABLE ELECTRONIC DEVICE
Granted: December 22, 2011
Application Number:
20110311853
A planar galvanic cell arrangement for portable electronic device is provided. In one embodiment, a galvanic cell arrangement may include a flexible substrate including a surface area that forms a plane. The galvanic cell arrangement also includes a plurality of galvanic cells coupled with the flexible substrate within the surface area that forms the plane, and electrically connected with one another in series, each of the plurality of galvanic cells including a negative electrode and a…
DIGITAL SIGNAL PROCESSING ARCHITECTURE SUPPORTING EFFICIENT CODING OF MEMORY ACCESS INFORMATION
Granted: December 22, 2011
Application Number:
20110314209
A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory…
PARITY-BASED RAID SYSTEM CONFIGURED TO PROTECT AGAINST DATA CORRUPTION CAUSED BY THE OCCURRENCE OF WRITE HOLES
Granted: December 22, 2011
Application Number:
20110314218
A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity…
LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS
Granted: December 8, 2011
Application Number:
20110298026
An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level…
Switching Clock Sources
Granted: December 8, 2011
Application Number:
20110298502
A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the…
ELECTRONIC DEVICE HAVING ELECTRICALLY GROUNDED HEAT SINK AND METHOD OF MANUFACTURING THE SAME
Granted: December 1, 2011
Application Number:
20110292612
An electronic device includes an integrated circuit (IC) package attached to a substrate and a heat sink attached to the IC package. Additionally, the electronic device also includes a film having an electric conductivity and contacting the heat sink and the IC package and extending to the substrate to provide a grounding connection for the heat sink. A method of manufacturing an electronic device includes connecting an IC package to a substrate, coupling a heat sink to the IC package…
DATA LATCH CIRCUIT AND METHOD OF A LOW POWER DECISION FEEDBACK EQUALIZATION (DFE) SYSTEM
Granted: November 24, 2011
Application Number:
20110286511
Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE)…
