THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION
Granted: May 2, 2013
Application Number:
20130105966
An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.
3D CHIP PACKAGE WITH SHIELDED STRUCTURES
Granted: May 2, 2013
Application Number:
20130105950
A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second…
SYSTEM AND METHOD FOR APPLYING MULTI-TONE OFDM BASED COMMUNICATIONS WITHIN A PRESCRIBED FREQUENCY RANGE
Granted: April 25, 2013
Application Number:
20130101057
According to one embodiment of the invention, an integrated circuit comprises an encoding module, a modulation module and a spectral shaped module. The encoding module includes an interleaver that adapted to operate in a plurality of modes including a first mode and a second mode. The interleaver performs repetitive encoding when placed in the second mode. The modulation module is adapted to compensate for attenuations that are to be realized during propagation of a transmitted signal…
Multilevel Class-D Amplifier
Granted: April 25, 2013
Application Number:
20130099859
A multilevel class-D differential amplifier which can be operated in at least three modes includes a first power stage and a second power stage. In an idle mode, an output of the first power stage varies between a first voltage level and a second voltage level, wherein an output of the second power stage varies between the first voltage level and the second voltage level. In a PWM mode, the output of the first power stage varies between the first voltage level and the second voltage…
Adaptive Motion Estimation Cache Organization
Granted: April 18, 2013
Application Number:
20130094570
In some embodiments, a motion estimation search window cache is adaptively re-organized according to frame properties including a frame width and a number of reference frames corresponding to the current frame to be encoded/decoded. The cache reorganization may include an adaptive mapping of reference frame locations to search window cache allocation units (addresses). In some embodiments, a search window is shaped as a quasi-rectangle with truncated upper left and lower right corners,…
SENDING DIGITAL DATA VISUALLY USING MOBILE DISPLAY AND CAMERA SENSOR
Granted: April 11, 2013
Application Number:
20130091548
A system for establishing a connection between a first device and a wireless network includes a first control module, located on the first device, that receives encoded digital data. The encoded digital data corresponds to a plurality of images displayed sequentially on a display of a second device. Each of the plurality of images corresponds to a different portion of the encoded digital data. A decoder module, located on the first device, converts the encoded digital data into…
Wafer Level Packaging Using a Lead-Frame
Granted: April 11, 2013
Application Number:
20130089953
Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips,…
SEMICONDUCTOR DEVICE HAVING DMOS INTEGRATION
Granted: April 11, 2013
Application Number:
20130087850
Semiconductor devices that include a trench with conductive material for connecting a VDMOS device to a LDMOS device are described. The semiconductor devices include a substrate having a first region and a second region, wherein the second region is disposed on the first region. A trench extends from a top surface of the second region to the first region. The semiconductor substrate includes a VDMOS device formed proximate to the top surface of the second region and a LDMOS device that…
DUAL-GATE VDMOS DEVICE
Granted: April 4, 2013
Application Number:
20130082321
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to…
Antibody Categorization Based on Binding Characteristics
Granted: April 4, 2013
Application Number:
20130085074
Methods for categorizing antibodies based on their epitope binding characteristics are described. Methods and systems for determining the epitope recognition properties of different antibodies are provided. Also provided are data analysis processes for clustering antibodies on the basis of their epitope recognition properties and for identifying antibodies having distinct epitope binding characteristics.
STRAPPED DUAL-GATE VDMOS DEVICE
Granted: April 4, 2013
Application Number:
20130082320
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to…
SOFT REPETITION CODE COMBINER USING CHANNEL STATE INFORMATION
Granted: March 28, 2013
Application Number:
20130077700
An embodiment is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. Another embodiment is a method and apparatus to decode a signal using averaging. A channel…
DIGITAL FREQUENCY DIVIDER
Granted: March 21, 2013
Application Number:
20130070832
Various embodiments of the present invention relate to systems, devices and method of frequency synthesis that generate in-phase and quadrature-phase clock signals at a programmable frequency. The generated frequency, which can range from a fraction to multiples of the input reference frequency, is generated by dividers following a phase-locked loop, thus avoiding the use of a low input reference frequency as well as frequency doubling.
STACKED WAFER-LEVEL PACKAGE DEVICE
Granted: March 7, 2013
Application Number:
20130056866
Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device includes one or more micro-solder bumps. The wafer-level package device further…
MULTI-MODE PARAMETER ANALYZER FOR POWER SUPPLIES
Granted: February 28, 2013
Application Number:
20130049723
A system includes an input selection module, a multiplier selection module, a multiplier module, an adding module, a plurality of accumulators, and an estimation module. The input selection module selects input signals including a duty cycle signal and current and voltage signals of a power supply. The multiplier selection module selects inputs from sine and cosine generator. The multiplier module multiplies the selected input signals by the inputs from the sine and cosine generator to…
LOAD COMPENSATION FOR AN ELECTRONIC TRANSFORMER IN A LED ILLUMINATION SYSTEM
Granted: February 28, 2013
Application Number:
20130049617
The invention relates to a light emitting diode (LED) illumination system, and more particularly, to systems, devices and methods of rapidly ramping up a transformer current and a LED driver current by coupling a transformer load compensation circuitry to an output of an electronic transformer. A bridge rectifier is coupled to the electronic transformer and provides full-wave rectification to an AC supply at the output of the electronic transformer. The load compensation circuitry senses…
SEMICONDUCTOR DEVICE HAVING A THROUGH-SUBSTRATE VIA
Granted: February 14, 2013
Application Number:
20130037948
Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer…
FAILSAFE GALVANIC ISOLATION BARRIER
Granted: February 7, 2013
Application Number:
20130033791
A system includes a transmitter, a receiver, a isolation barrier, and a fuse. The isolation barrier is connected to the transmitter. The fuse is connected between the isolation barrier and the receiver. The isolation barrier prevents current flow from the transmitter to the receiver when a voltage across the isolation barrier is less than a first breakdown voltage. The isolation barrier short circuits when the voltage across the isolation barrier is greater than or equal to the first…
MICRO-GYROSCOPE FOR DETECTING MOTIONS
Granted: February 7, 2013
Application Number:
20130031977
The invention relates to a micro-gyroscope for detecting motions relative to an X and/or Y and Z axis, particularly as a 3D, 5D, or 6D sensor. Sample masses are disposed uniformly about an anchor and can be driven radially relative to the central anchor. Anchor springs are disposed to attach the sample masses to a substrate, and these sample masses can be deflected both radially within and out of the X-Y plane. A sensor mass is disposed on one of the sample masses by means of sensor…
FULL-DUPLEX SINGLE-ENDED SERIAL LINK COMMUNICATION SYSTEM
Granted: January 24, 2013
Application Number:
20130021953
A system for full duplex communication using a single-ended communications link is described. The system includes a first link interface configured to generate a signal for transmission via the single-ended communications link. The signal includes data encoded in a forward channel. The system also includes a second link interface configured to receive the signal from the first link interface via the single-ended communications link and modulate the signal to encode data in a reverse…
