EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL
Granted: January 15, 2009
Application Number:
20090014772
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is…
Plasma Systems with Magnetic Filter Devices to Alter Film Deposition/Etching Characteristics
Granted: December 4, 2008
Application Number:
20080296143
Plasma systems with magnetic filter devices to alter film deposition/etching characteristics by altering the effective magnetic field distribution. The magnetic filter devices are placed between the magnet or magnets and a target, typically a semiconductor wafer, and selected and configured to alter the magnetic field to obtain the desired processing results. For deposition, the magnetic filter may be chosen to provide more uniform deposition, to provide increased deposition rates at or…
METHOD OF PROGRAMMING A SELECTED MEMORY CELL
Granted: November 6, 2008
Application Number:
20080273392
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is…
METHOD OF ERASING A BLOCK OF MEMORY CELLS
Granted: November 6, 2008
Application Number:
20080273401
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is…
EEPROM MEMORY DEVICE WITH CELL HAVING NMOS IN A P POCKET AS A CONTROL GATE, PMOS PROGRAM/ERASE TRANSISTOR, AND PMOS ACCESS TRANSISTOR IN A COMMON WELL
Granted: September 18, 2008
Application Number:
20080225601
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is…
Bragg mirror optimized for shear waves
Granted: August 28, 2008
Application Number:
20080204857
In an embodiment, set forth by way of example and not limitation, a Bragg mirror includes a first bi-layer of a first thickness and a second bi-layer of a second thickness which is different from the first thickness. In this exemplary embodiment, the first bi-layer consists essentially of a first high impedance layer and a first low impedance layer, and the second bi-layer of a second thickness which is different from the first thickness, the second bi-layer consisting essentially of a…
SINGLE-SIDED, FLAT, NO LEAD, INTEGRATED CIRCUIT PACKAGE
Granted: August 21, 2008
Application Number:
20080197504
An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The…
System and method for using an output transformer for laser diode drivers
Granted: December 23, 2004
Application Number:
20040258114
A laser diode driver output stage for driving an associated laser diode device. The laser diode driver output stage includes a driver circuit adapted to receive an input data signal at an input node and provide an output signal to a positive output node and a negative output node in response to the data signal. The laser diode driver output stage further includes a transformer having a positive terminal of a first side coupled to the positive output node of the driver circuit, a negative…
System and method for using an output transformer for packaged laser diode drivers
Granted: December 23, 2004
Application Number:
20040258115
A laser diode driver output stage for driving an associated laser diode device. In one aspect of the present invention, the laser diode driver output stage includes a driver circuit having at least one input node and an output node. The driver circuit is adapted to receive an input data signal at the at least one input node and provide an output signal at the output node in response to the data signal. The laser diode driver output stage further includes a transformer connected to the…
