Robust ramp controlled enable for voltage regulator
Granted: January 2, 2007
Patent Number:
7157892
A voltage regulator including a bandgap control circuit that maintains the regulator's bandgap voltage at a predetermined voltage level after an externally generated enable signal is de-asserted until the regulated output voltage has dropped below a predetermined low reference voltage. The bandgap control circuit includes a latch that is set by the enable control signal to generate a bandgap control signal, which is used to activate a bandgap reference generator that generates the…
Dual mode buck regulator with improved transition between LDO and PWM operation
Granted: December 12, 2006
Patent Number:
7148670
A dual mode regulator, having a high current PWM regulator mode and a low current LDO regulator mode, briefly changes the operating parameters of the PWM and LDO regulators during a transition between modes. Changes during the transition period include: raising the error amplifier reference voltage of the LDO or PWM regulator to ensure a definite handover, raising the bias current in the LDO stages during the transition to cause the LDO regulator to quickly and stably respond to voltage…
MOS field effect transistor with reduced parasitic substrate conduction
Granted: December 5, 2006
Patent Number:
7145206
A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasitic bipolar transistor having the effect of reducing substrate conduction caused by a forward biased drain to body junction.
Seal ring for mixed circuitry semiconductor devices
Granted: December 5, 2006
Patent Number:
7145211
In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
Lateral programmable polysilicon structure incorporating polysilicon blocking diode
Granted: December 5, 2006
Patent Number:
7145255
A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable…
Control circuit for monitoring and maintaining a bootstrap voltage in an N-channel buck regulator
Granted: December 5, 2006
Patent Number:
7145316
A control circuit is incorporated in a switching regulator for monitoring and maintaining a bootstrap voltage to allow the switching regulator to operate at or near 100% duty cycle. The control circuit includes a circuit receiving the bootstrap voltage and generating a monitor voltage, a comparator circuit receiving the monitor voltage and a first voltage indicative of a switching output voltage and generating an output signal having a first state when the monitor voltage is equal to or…
Timer circuit with adaptive reference
Granted: November 21, 2006
Patent Number:
7138843
A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and…
Non-synchronous boost converter including switched schottky diode for true disconnect
Granted: October 24, 2006
Patent Number:
7126314
A non-synchronous boost converter includes a switched Schottky diode to rectify the switched output voltage of the boost converter where the switched Schottky diode has forward conduction blocking capability. The switched Schottky diode has an anode terminal coupled to receive the switched output voltage, a cathode terminal providing the output DC voltage, and a gate terminal coupled to receive a control signal. The control signal has a first state for turning the switched Schottky diode…
Analog control of a digital decision process
Granted: October 24, 2006
Patent Number:
7126513
A circuit and method for programming and control of an integrated circuit includes a control pin receiving an applied input voltage selected from a set of predetermined programming voltages and an on-chip control voltage decode circuit to select one of multiple programming states for the integrated circuit based on the applied input voltage. In one embodiment, an off-chip voltage divider is used to establish the set of predetermined programming voltages. The on-chip control voltage…
Method and system for multichannel-isolation-technique multiplexer
Granted: October 17, 2006
Patent Number:
7123074
A multiplexer is disclosed. The multiplexer comprises a first input and a first channel coupled to the first input. The multiplexer further includes a second input and a second channel coupled to the second input. Finally, the multiplexer includes an output coupled to the first and second channels, wherein a coupling capacitance of an inactive one of the first and second channels is not coupled directly to the output. A method and system in accordance with the present invention reduces…
Electrostatic discharge protection device comprising several thyristors
Granted: September 26, 2006
Patent Number:
7113377
An electrostatic discharge protection device comprises several thyristors which are connected in parallel between two nodes of an electrical circuit. It also includes a control circuit having an output connected to the control trigger terminal input of each of the thyristors. In response to an abnormal variation in a voltage between the two nodes being detected, the control circuit initiates a triggering current on the output so as to trigger the thyristors to conduct current between the…
Method and system for providing a CMOS output stage utilizing a buried power buss
Granted: September 5, 2006
Patent Number:
7102167
A CMOS output stage is disclosed. The CMOS output stage comprises a substrate and at least one well coupled to the substrate. The CMOS output stage also includes a plurality of slots provided through the one well into the substrate. Each of the slots are oxidized. Each of the plurality of slots are filled with metal to provide a plurality of power busses. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power…
Programming and control of an integrated circuit using an externally connected resistor network
Granted: September 5, 2006
Patent Number:
7102394
A circuit in an integrated circuit having input terminals coupled to a resistor network for selecting one of multiple digital states includes a tri-state circuit, a multiplexer, a comparator and a control circuit. A DAC can be used to generate a set of comparison voltage levels. The circuit detects the power connection and the resistance values of at least two resistors in the resistor network having a third resistor of fixed resistance. The resistance values for the two resistors are…
Method and system for providing a power lateral PNP transistor using a buried power buss
Granted: August 29, 2006
Patent Number:
7098113
A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5…
Method and system for vertical DMOS with slots
Granted: August 8, 2006
Patent Number:
7087491
A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted…
Ballast resistors for transistor devices
Granted: August 8, 2006
Patent Number:
7087973
A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors,…
High efficiency linear regulator
Granted: August 1, 2006
Patent Number:
7084612
A single chip hybrid regulator is disclosed having a first stage being a switching regulator and a second stage being a linear regulator. The switching regulator uses a filter circuit including an inductor and a capacitor. To make the hybrid regulator very small, the inductor value is selected so that the inductor saturates at a current level well below the maximum load current for the regulator. At low load currents, the small inductor does not saturate, and the regulated voltage…
Method and system for a programmable electrostatic discharge (ESD) protection circuit
Granted: July 25, 2006
Patent Number:
7081654
An electrostatic discharge (ESD) protection device is disclosed. The ESD protection device comprises a source diffusion in a substrate and a deeper body diffusion in the substrate. The ESD protection device further includes a gate function provided at a space between the source diffusion and the body diffusion surface terminations; and further includes a drain located a predetermined distance from the body diffusion. Finally, the ESD protection device includes a structure for shorting…
Precision PTAT current source using only one external resistor
Granted: July 11, 2006
Patent Number:
7075281
A current source for providing a current proportional to absolute temperature (a PTAT current) with high precision is implemented using only one off-chip component. The current source utilizes a bandgap voltage, a voltage related to a current proportional to absolute temperature and a constant current to bias a pair of voltage controlled resistive devices. In operation, a known resistance is derived by applying a constant voltage across and a constant current through a first voltage…
Overcurrent protection circuit with fast current limiting control
Granted: July 11, 2006
Patent Number:
7075373
An overcurrent protection circuit for a power transistor includes a transconductance amplifier and a bias current circuit. The transconductance amplifier receives a first signal indicative of the magnitude of the load current conducted by the power transistor and a reference voltage and provides a second signal for controlling the load current. The transconductance amplifier further provides a third signal having a first logical state indicating normal operation and a second logical…
