FERROMAGNETIC MATERIAL BASED INTEGRATED INDUCTOR IN SILICON
Granted: November 14, 2024
Application Number:
20240379731
A process for manufacturing inductors for use in integrated circuits includes embedding ferromagnetic material in a bulk silicon substrate, forming a plurality of vias in the bulk silicon substrate such that the vias bracket a volume of the bulk silicon substrate that includes the ferromagnetic material, slicing the bulk silicon substrate to form a silicon wafer, and configuring traces between top metal pads of the vias and between bottom metal pads of the vias to form a continuous path…
SYNTHETIC DATA GENERATION USING VIEWPOINT AUGMENTATION FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: October 31, 2024
Application Number:
20240362897
In various examples, systems and methods are disclosed relating to synthetic data generation using viewpoint augmentation for autonomous and semi-autonomous systems and applications. One or more circuits can identify a set of sequential images corresponding to a first viewpoint and generate a first transformed image corresponding to a second viewpoint using a first image of the set of sequential images as input to a machine-learning model. The one or more circuits can update the…
Chip Die Substrate with Edge-Mounted Capacitors
Granted: October 3, 2024
Application Number:
20240332223
An integrated circuit die substrate has one or more capacitors attached to an edge surface of the substrate. The substrate has a top surface and a bottom surface, at least one of which includes a die mounting area, and at least one of which includes system interconnect terminals. A substrate edge surface is disposed along a peripheral end of the substrate and is oriented substantially orthogonally to the top and bottom surfaces. A pair of conductive edge terminals is disposed on the…
ON DIE CURRENT SINK CIRCUIT FOR OVERSHOOT MITIGATION
Granted: September 26, 2024
Application Number:
20240322559
An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.
DECIDER NETWORKS FOR REACTIVE DECISION-MAKING FOR ROBOTIC SYSTEMS AND APPLICATIONS
Granted: September 26, 2024
Application Number:
20240319713
In various examples, systems and methods are disclosed relating to decider networks for reactive decision-making, including for control of robotic systems. The decider networks can allow robotic systems to operate more collaboratively, such as by allowing the robotic systems to more frequently process and react to dynamic states of the environment and objects in the environment, such as to change decisions and/or paths of decision execution responsive to dynamic changes in logical…
DATA AUGMENTATION FOR MODEL TRAINING IN AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: September 19, 2024
Application Number:
20240312123
In various examples, systems and methods are disclosed that relate to data augmentation for training/updating perception models in autonomous or semi-autonomous systems and applications. For example, a system may receive data associated with a set of frames that are captured using a plurality of cameras positioned in fixed relation relative to the machine; generate a panoramic view based at least on the set of frames; provide data associated with the panoramic view to a model to cause…
PROCESSOR ARCHITECTURE FOR OPTIMIZED PARALLELIZED SEARCH
Granted: September 12, 2024
Application Number:
20240303085
Systems and methods in accordance with the present disclosure can implement a parallel processing system, such as a graphics processing unit (GPU)-based system, to generate solutions to complex computational problems. Aspects of this technical solution can retrieve a plurality of solutions each representing a plurality of values in a multi-dimensional space, allocate, to one or more processing units associated with the one or more circuits and having a parallelized configuration, one or…
LOGIC CELL PLACEMENT MECHANISMS FOR IMPROVED CLOCK ON-CHIP VARIATION
Granted: September 5, 2024
Application Number:
20240296274
Mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. The resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.
SYSTEM FOR IMPLEMENTING MUTABLE DEVICE OWNERSHIP TRANSFER (DOT) OF A DEVICE
Granted: August 22, 2024
Application Number:
20240281514
Systems and methods are described herein for implementing a mutable device ownership transfer (DOT) of a device. An example system receives a request from a first customer to record a mutable DOT of a device using a First Customer Authentication Key (FCAK); receives the FCAK from the first customer in response to receiving the request; determines whether the device is capable of recording the mutable DOT; and installs, using a DOT circuitry, the FCAK in a non-volatile memory of a Root of…
VIA-BASED INDUCTOR COIL FOR INTEGRATED SILICON APPLICATIONS
Granted: August 8, 2024
Application Number:
20240266106
Integrated inductors are formed by arranging multiple vias to bracket a volume of semiconductor substrate, where each via includes a top metal pad and a bottom metal pad. The vias are alternately connected by way of the top and bottom pads to form an end-to-end current loop along a length of the volume of semiconductor substrate.
TRANSIENT CURRENT-MODE SIGNALING SCHEME FOR ON-CHIP INTERCONNECT FABRICS
Granted: August 8, 2024
Application Number:
20240264625
Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.
UNSUPERVISED PRE-TRAINING OF NEURAL NETWORKS USING GENERATIVE MODELS
Granted: August 1, 2024
Application Number:
20240256831
In various examples, systems and methods are disclosed relating to generating a response from image and/or video input for image/video-based artificial intelligence (AI) systems and applications. Systems and methods are disclosed for a first model (e.g., a teacher model) distilling its knowledge to a second model (a student model). The second model receives a downstream image in a downstream task and generates at least one feature. The first model generates first features corresponding…
DEVICE FOR COOLANT LEAK DETECTION ON PRINTED CIRCUIT BOARDS
Granted: July 18, 2024
Application Number:
20240241007
Devices, systems, and methods are provided for surface-mounted leak detection on a printed circuit board. An example leak detection device includes a first and second electrical contact with a selectively conductive material disposed therebetween. At a first electrical conductivity of the selectively conductive material, the device has a first circuit state. The selectively conductive material is configured to change from the first electrical conductivity to a second electrical…
DIGITALLY CONTROLLED UNIFIED RECEIVER FOR MULTI-RANK SYSTEM
Granted: July 11, 2024
Application Number:
20240235557
A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply an analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to…
IMAGE PROCESSING USING NEURAL NETWORKS, WITH IMAGE REGISTRATION
Granted: July 11, 2024
Application Number:
20240233146
In various examples, systems and methods are disclosed relating to registering image processing with image registration for image generation and content stream applications. Systems and methods are disclosed for registering portions of images that are modified to incorporate content or features, with references images from which the portions of the images are identified. The systems and methods can transform the modified portions to more realistically and precisely merge back into the…
ALLOCATING RADIO RESOURCES USING ARTIFICIAL INTELLIGENCE
Granted: July 4, 2024
Application Number:
20240223344
Apparatuses, systems, and techniques to allocate one or more compute resources to a user device. In at least one embodiment, one or more circuits cause one or more compute resources to be allocated to two or more fifth-generation (5G) radio access network (RAN) cells based, at least in part, on interference between the two or more 5G RAN cells.
DETERMINING OBJECT ASSOCIATIONS USING MACHINE LEARNING IN AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: June 27, 2024
Application Number:
20240211748
In various examples, systems and methods are disclosed relating to determining associations between objects represented in sensor data and predicted states of the objects in multi-sensor systems such as autonomous or semi-autonomous vehicle perception systems. Systems and methods are disclosed that employ neural network models, such as multi-layer perceptron (MLP) models or other deep neural network (DNN) models, in learning association costs between sensor measurements and predicted…
ALIAS-FREE TAGGED ERROR CORRECTING CODES FOR MACHINE MEMORY OPERATIONS
Granted: June 6, 2024
Application Number:
20240184670
Implicit Memory Tagging (IMT) mechanisms utilizing alias-free memory tags that enable hardware-assisted memory tagging without incurring storage overhead above those incurred by conventional tagging mechanisms, while providing enhanced data integrity and memory security. The IMT mechanisms enhance the utility of error correcting codes (ECCs) to test memory tags in addition to the traditional utility of ECCs for detecting and correcting data errors and enable a finer granularity of memory…
VISION TRANSFORMER FOR IMAGE GENERATION
Granted: June 6, 2024
Application Number:
20240185396
Apparatuses, systems, and techniques to generate images. In at least one embodiment, one or more machine learning models generate an output image based, at least in part, on calculating attention scores using time embeddings.
GENERATING VARIATIONAL DIALOGUE RESPONSES FROM STRUCTURED DATA FOR CONVERSATIONAL AI SYSTEMS AND APPLICATIONS
Granted: June 6, 2024
Application Number:
20240184991
In various examples, systems and methods are disclosed relating to generating dialogue responses from structured data for conversational artificial intelligence (AI) systems and applications. Systems and methods are disclosed for training or updating a machine learning model—such as a deep neural network—for deployment using structured data from dialogues of multiple domains. The systems and methods can generate responses to users to provide a more natural user experience, such as by…
