SMALL MOLECULE GENERATION USING MACHINE LEARNING MODELS
Granted: February 20, 2025
Application Number:
20250061978
In various examples, systems and methods are disclosed relating to using machine learning models to generate small molecules with desired structural or physicochemical properties with high sampling efficiency. In some implementations, one or more processors receive a data structure representing a first small molecule and encode the data structure into a latent distribution of a fixed size using a machine learning model, thereby determining an encoded representation of the data structure.…
NEURAL NETWORKS FOR SYNTHETIC DATA GENERATION WITH DISCRETE AND CONTINUOUS VARIABLE FEATURES
Granted: February 20, 2025
Application Number:
20250061612
In various examples, systems and methods are disclosed relating to neural networks for synthetic data generation with discrete and continuous variable features. In training, an encoder can determine a plurality of encodings from a plurality of samples of training data, and the continuous generative model can operate as a decoder that is conditioned on the plurality of encodings to generate an estimated output to update the encoder and the continuous generative model. The discrete…
UPDATING SYNTHETIC IMAGE LABELS USING NEURAL NETWORKS TO IMPROVE PERFORMANCE ON REAL-WORLD APPLICATIONS
Granted: February 13, 2025
Application Number:
20250054288
Various examples relate to translating image labels from one domain (e.g., a synthetic domain) to another domain (e.g., a real-world domain) to improve model performance on real-world datasets and applications. Systems and methods are disclosed that provide an unsupervised label translator that may employ a generative adversarial network (GAN)-based approach. In contrast to conventional systems, the disclosed approach can employ a data-centric perspective that addresses systematic…
THREE DIMENSIONAL CIRCUIT MOUNTING STRUCTURES
Granted: February 6, 2025
Application Number:
20250048532
A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.
SURFACE TEXTURE GENERATION FOR THREE-DIMENSIONAL OBJECT MODELS USING GENERATIVE MACHINE LEARNING MODELS
Granted: February 6, 2025
Application Number:
20250045980
Aspects of this technical solution can obtain, according to a plurality of cameras oriented toward the surface of a three-dimensional (3D) model having a surface including a two-dimensional (2D) texture model, input according to corresponding views from the plurality of cameras of the 2D texture model on the surface of the 3D model, and generate, according to the input and according to a model configured to generate a two-dimensional (2D) image, an output including a 2D texture for the…
REAL-TIME MULTIPLE VIEW MAP GENERATION USING NEURAL NETWORKS
Granted: February 6, 2025
Application Number:
20250045952
In various examples, systems and methods are disclosed relating to real-time multiview map generation using neural networks. A system can receive sensors images of an environment, such as images from one or more camera, RADAR, LIDAR, and/or ultrasound sensors. The system can process the sensor images using one or more neural networks, such as neural networks implementing attention structures, to detect features in the environment such as lane lines, lane dividers, wait lines, or…
ACCELERATED GEOMETRY PROCESSING USING PARALLEL PROCESSING SYSTEMS
Granted: January 30, 2025
Application Number:
20250037376
In various examples, systems and methods are disclosed relating to shape processing using parallel computing systems. A processor can map one or more combinations of a plurality of first polygons identified from a first structure and a plurality of second polygons identified from a second structure, to a grid comprising a plurality of cells. The processor can identify one or more occupied cells of the plurality of cells, to which the one or more combinations are mapped. The processor can…
DENOISING DYNAMICALLY RAY-TRACED SCENES USING TEMPORAL AND SPATIAL VARIANCES OF HISTORICAL PIXEL VALUES
Granted: January 23, 2025
Application Number:
20250029315
In various examples, systems and methods are disclosed relating to historical reset. One method includes determining at least one history buffer for a frame, determining, in a spatial domain, a spatial component of the accumulated pixel value at the pixel location based on a first spatial moment and a second spatial moment, determining, in a temporal domain, a temporal component of the accumulated pixel value at the pixel location based on a first temporal moment and a second temporal…
DENOISING DYNAMICALLY RAY-TRACED SCENES USING HISTORICAL PIXEL VALUES
Granted: January 23, 2025
Application Number:
20250029204
In various examples, systems and methods are disclosed relating to historical acceleration. One method includes determining a plurality of history buffers for a frame, the plurality of history buffers comprising a responsive history buffer and a normal history buffer, the responsive history buffer comprising a first pixel value at a pixel location of the frame, and the normal history buffer comprising a second pixel value at the pixel location of the frame, and the normal history buffer…
MULTI-MODAL SYNTHETIC CONTENT GENERATION USING NEURAL NETWORKS
Granted: January 16, 2025
Application Number:
20250022100
In various examples, systems and methods are disclosed relating to systems and methods for multi-modal creative content generation using neural networks. The systems and methods can use one or more neural networks to generate outputs representative of creative and/or artistic characteristics of features indicated by input prompts. The one or more neural networks can include at least one text extension model to increase an amount of information of the input prompts. The one or more neural…
CIRCUIT TO PROTECT AGAINST MULTI-RAIL VOLTAGE GLITCHING ATTACKS
Granted: January 2, 2025
Application Number:
20250004522
A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first…
BACKLIGHT-FREE AUGMENTED REALITY USING DIGITAL HOLOGRAPHY
Granted: January 2, 2025
Application Number:
20250004275
Optical systems including an interferometer utilizing a spatial light modulator. A light guide including a first beam splitter and multiple mirrors directs incoherent light through the beam splitter to the interferometer to generate an interference light pattern, and further directs the interference light pattern back to the first beam splitter via the mirrors.
SHARED METAL WIRE CAPACITANCE FOR NEGATIVE BIT-LINE
Granted: December 19, 2024
Application Number:
20240420748
Negative bit line voltage assist mechanisms for multi-bank machine memories utilizing multiple local IO drivers include a shared boost capacitor configured to generate a negative bit line voltage assist for write operations by local IO drivers, where the boost capacitor is configured to selectively couple to one of the local IO drivers during the write operation.
DYNAMIC STANDARD CELL EXTERNAL PIN METHODOLOGY FOR ROUTABILITY-DRIVEN STANDARD CELL DESIGN AUTOMATION
Granted: December 12, 2024
Application Number:
20240411977
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during…
PIN DENSITY-BASED CONGESTION ESTIMATION FOR ROUTABILITY-DRIVEN STANDARD CELL SYNTHESIS
Granted: December 12, 2024
Application Number:
20240411974
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during…
VOLTAGE REGULATOR DROOP REDUCTION MECHANISM
Granted: December 5, 2024
Application Number:
20240402740
Power supply circuits in which a supplemental current driver is utilized to boost the current provided by a voltage regulator. The supplementing driver detects operating conditions for providing the supplementary current, and may be trained to provide particular amounts of current in response to particular operation conditions of a circuit load.
DETERMINING OBSTACLE PERCEPTION SAFETY ZONES FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: December 5, 2024
Application Number:
20240400101
In various examples, systems and methods are disclosed relating to refinement of safety zones and improving evaluation metrics for the perception modules of autonomous and semi-autonomous systems. Example implementations can exclude areas in the state space that are not safety critical, while retaining the areas that are safety-critical. This can be accomplished by leveraging ego maneuver information and conditioning safety zone computations on ego maneuvers. A maneuver-based…
CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL
Granted: November 28, 2024
Application Number:
20240395293
Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the…
METHOD FOR INTEGRATING A COPPER-GRAPHENE LAMINATE (CGL) IN A MULTILAYER PCB FABRICATION PROCESS
Granted: November 28, 2024
Application Number:
20240397636
Methods for integrating copper-graphene laminate (CGL) in a multilayer PCB fabrication process and the resulting lamination stacks are disclosed. The methods include providing a core and applying a first graphene layer to the surface of the core. The methods further include applying a metal layer to the first graphene layer and applying a second graphene layer to the metal layer. Further, the methods include applying a photoresist layer to the second graphene layer and applying a…
GRAPHENE INTEGRATED CORE AND ASSOCIATED METHODS FOR THERMAL MANAGEMENT WITHIN PRINTED CIRCUIT BOARDS
Granted: November 28, 2024
Application Number:
20240397604
Methods of forming a graphene integrated core for making a printed circuit board (PCB) having enhanced thermal management properties are disclosed. The methods include providing a core body having a core body length and applying a graphene multi-layer to the core body to form a laminated stack, where the graphene multi-layer has a graphene multi-layer length that is shorter than the core body length. At least one conductive layer may be applied to the laminated stack. The graphene…
