SYNTHETIC DATASET GENERATOR
Granted: April 18, 2024
Application Number:
20240127075
Machine learning is a process that learns a model from a given dataset, where the model can then be used to make a prediction about new data. In order to reduce the costs associated with collecting and labeling real world datasets for use in training the model, computer processes can synthetically generate datasets which simulate real world data. The present disclosure improves the effectiveness of such synthetic datasets for training machine learning models used in real world…
GENERATIVE MACHINE LEARNING MODELS FOR PRIVACY PRESERVING SYNTHETIC DATA GENERATION USING DIFFUSION
Granted: April 4, 2024
Application Number:
20240111894
In various examples, systems and methods are disclosed relating to differentially private generative machine learning models. Systems and methods are disclosed for configuring generative models using privacy criteria, such as differential privacy criteria. The systems and methods can generate outputs representing content using machine learning models, such as diffusion models, that are determined in ways that satisfy differential privacy criteria. The machine learning models can be…
Detection of Electromagnetic Fault Injection Attacks on Digital Systems
Granted: March 28, 2024
Application Number:
20240104252
Techniques are described for detecting an electromagnetic (“EM”) fault injection attack directed toward circuitry in a target digital system. In various embodiments, a first node may be coupled to first driving circuitry, and a second node may be coupled to second driving circuitry. The driving circuitry is implemented in a manner such that a logic state on the second node has greater sensitivity to an EM pulse than has a logic state on the first node. Comparison circuitry may be…
REDUCING FALSE POSITIVE RAY TRAVERSAL USING RAY CLIPPING
Granted: March 21, 2024
Application Number:
20240095995
Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS
Granted: March 21, 2024
Application Number:
20240094291
A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.
PROCESSOR-BASED STORAGE ALLOCATION
Granted: February 29, 2024
Application Number:
20240069767
Apparatuses, systems, and techniques to allocate portions of a storage to groups of processors. In at least one embodiment, an amount of storage to store data to be used by one or more computer programs, based at least in part, on an amount of processors to perform one or more portions of the one or more computer programs.
SCHEDULING INSTRUCTIONS USING LATENCY OF INTERCONNECTS OF PROCESSORS
Granted: February 29, 2024
Application Number:
20240069964
Apparatuses, systems, and techniques for scheduling instructions in a cluster to guarantee GPU-CPU alignment for these instructions. In at least one embodiment, jobs are scheduled based on constraints on job sizes and job placement. In at least one embodiment, a processor comprises circuits to schedule instructions to be performed by processors based on latency of interconnects coupled to these processors.
USING PAST PERFORMANCE OF COMPUTING RESOURCES TO PERFORM SOFTWARE PROGRAMS
Granted: February 29, 2024
Application Number:
20240069998
Apparatuses, systems, and techniques for selecting computing resources based on software programs scoring past performance of computing resources. In at least one embodiment, a processor comprising circuitry may cause software programs to be performed using computing resources based on software programs to score past performance of the one or more computing resources. In at least one embodiment, a processor selects a computing system to perform a software workload based on attributes of…
TECHNIQUES TO OBTAIN METRICS DATA
Granted: February 29, 2024
Application Number:
20240070798
Apparatuses, systems, and techniques to obtain metric data of a computing resource service provider. In at least one embodiment, metric data of one or more graphics processing unit (GPUs) is caused to be obtained from the one or more GPUs in an order from newest to oldest.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030916
A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030917
Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030918
Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030916
A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030917
Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030918
Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
LARGE SCALE MASK OPTIMIZATION WITH CONVOLUTIONAL FOURIER NEURAL OPERATOR AND LITHO-GUIDED SELF LEARNING
Granted: January 11, 2024
Application Number:
20240013033
A circuit mask optimizer utilizes a Convolutional Fourier Neural Operator (CFNO) to efficiently learn layout tile dependencies, enabling stitch-less largescale mask optimization with limited intervention of legacy tools. Litho-guided self training via a trained machine learning model provides non-convex optimization, enabling iterative model and dataset refinements at a substantial performance improvement over conventional solutions.
LARGE SCALE MASK OPTIMIZATION WITH CONVOLUTIONAL FOURIER NEURAL OPERATOR AND LITHO-GUIDED SELF LEARNING
Granted: January 11, 2024
Application Number:
20240013033
A circuit mask optimizer utilizes a Convolutional Fourier Neural Operator (CFNO) to efficiently learn layout tile dependencies, enabling stitch-less largescale mask optimization with limited intervention of legacy tools. Litho-guided self training via a trained machine learning model provides non-convex optimization, enabling iterative model and dataset refinements at a substantial performance improvement over conventional solutions.
REDUCING LEVEL OF DETAIL OF A POLYGON MESH TO DECREASE A COMPLEXITY OF RENDERED GEOMETRY WITHIN A SCENE
Granted: December 28, 2023
Application Number:
20230419611
A method, computer readable medium, and system are disclosed for overlaying a cell onto a polygon meshlet. The polygon meshlet may include a grouping of multiple geometric shapes such as triangles, and the cell may include a square-shaped boundary. Additionally, every polygon (e.g., a triangle or other geometric shape) within the polygon meshlet that has at least one edge fully inside the cell is removed to create an intermediate meshlet. A selected vertex is determined from all vertices…
HARDWARE-EFFICIENT PAM-3 ENCODER AND DECODER
Granted: December 28, 2023
Application Number:
20230418705
A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the…
STAGGERED DUAL-SIDE MULTI-CHIP INTERCONNECT
Granted: December 21, 2023
Application Number:
20230411365
Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.
