DENOISING DYNAMICALLY RAY-TRACED SCENES USING TEMPORAL AND SPATIAL VARIANCES OF HISTORICAL PIXEL VALUES
Granted: January 23, 2025
Application Number:
20250029315
In various examples, systems and methods are disclosed relating to historical reset. One method includes determining at least one history buffer for a frame, determining, in a spatial domain, a spatial component of the accumulated pixel value at the pixel location based on a first spatial moment and a second spatial moment, determining, in a temporal domain, a temporal component of the accumulated pixel value at the pixel location based on a first temporal moment and a second temporal…
DENOISING DYNAMICALLY RAY-TRACED SCENES USING HISTORICAL PIXEL VALUES
Granted: January 23, 2025
Application Number:
20250029204
In various examples, systems and methods are disclosed relating to historical acceleration. One method includes determining a plurality of history buffers for a frame, the plurality of history buffers comprising a responsive history buffer and a normal history buffer, the responsive history buffer comprising a first pixel value at a pixel location of the frame, and the normal history buffer comprising a second pixel value at the pixel location of the frame, and the normal history buffer…
MULTI-MODAL SYNTHETIC CONTENT GENERATION USING NEURAL NETWORKS
Granted: January 16, 2025
Application Number:
20250022100
In various examples, systems and methods are disclosed relating to systems and methods for multi-modal creative content generation using neural networks. The systems and methods can use one or more neural networks to generate outputs representative of creative and/or artistic characteristics of features indicated by input prompts. The one or more neural networks can include at least one text extension model to increase an amount of information of the input prompts. The one or more neural…
CIRCUIT TO PROTECT AGAINST MULTI-RAIL VOLTAGE GLITCHING ATTACKS
Granted: January 2, 2025
Application Number:
20250004522
A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first…
BACKLIGHT-FREE AUGMENTED REALITY USING DIGITAL HOLOGRAPHY
Granted: January 2, 2025
Application Number:
20250004275
Optical systems including an interferometer utilizing a spatial light modulator. A light guide including a first beam splitter and multiple mirrors directs incoherent light through the beam splitter to the interferometer to generate an interference light pattern, and further directs the interference light pattern back to the first beam splitter via the mirrors.
SHARED METAL WIRE CAPACITANCE FOR NEGATIVE BIT-LINE
Granted: December 19, 2024
Application Number:
20240420748
Negative bit line voltage assist mechanisms for multi-bank machine memories utilizing multiple local IO drivers include a shared boost capacitor configured to generate a negative bit line voltage assist for write operations by local IO drivers, where the boost capacitor is configured to selectively couple to one of the local IO drivers during the write operation.
DYNAMIC STANDARD CELL EXTERNAL PIN METHODOLOGY FOR ROUTABILITY-DRIVEN STANDARD CELL DESIGN AUTOMATION
Granted: December 12, 2024
Application Number:
20240411977
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during…
PIN DENSITY-BASED CONGESTION ESTIMATION FOR ROUTABILITY-DRIVEN STANDARD CELL SYNTHESIS
Granted: December 12, 2024
Application Number:
20240411974
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during…
DETERMINING OBSTACLE PERCEPTION SAFETY ZONES FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: December 5, 2024
Application Number:
20240400101
In various examples, systems and methods are disclosed relating to refinement of safety zones and improving evaluation metrics for the perception modules of autonomous and semi-autonomous systems. Example implementations can exclude areas in the state space that are not safety critical, while retaining the areas that are safety-critical. This can be accomplished by leveraging ego maneuver information and conditioning safety zone computations on ego maneuvers. A maneuver-based…
VOLTAGE REGULATOR DROOP REDUCTION MECHANISM
Granted: December 5, 2024
Application Number:
20240402740
Power supply circuits in which a supplemental current driver is utilized to boost the current provided by a voltage regulator. The supplementing driver detects operating conditions for providing the supplementary current, and may be trained to provide particular amounts of current in response to particular operation conditions of a circuit load.
METHOD FOR INTEGRATING A COPPER-GRAPHENE LAMINATE (CGL) IN A MULTILAYER PCB FABRICATION PROCESS
Granted: November 28, 2024
Application Number:
20240397636
Methods for integrating copper-graphene laminate (CGL) in a multilayer PCB fabrication process and the resulting lamination stacks are disclosed. The methods include providing a core and applying a first graphene layer to the surface of the core. The methods further include applying a metal layer to the first graphene layer and applying a second graphene layer to the metal layer. Further, the methods include applying a photoresist layer to the second graphene layer and applying a…
GRAPHENE INTEGRATED CORE AND ASSOCIATED METHODS FOR THERMAL MANAGEMENT WITHIN PRINTED CIRCUIT BOARDS
Granted: November 28, 2024
Application Number:
20240397604
Methods of forming a graphene integrated core for making a printed circuit board (PCB) having enhanced thermal management properties are disclosed. The methods include providing a core body having a core body length and applying a graphene multi-layer to the core body to form a laminated stack, where the graphene multi-layer has a graphene multi-layer length that is shorter than the core body length. At least one conductive layer may be applied to the laminated stack. The graphene…
CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL
Granted: November 28, 2024
Application Number:
20240395293
Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the…
SCENE UNDERSTANDING USING LANGUAGE MODELS FOR ROBOTICS SYSTEMS AND APPLICATIONS
Granted: November 21, 2024
Application Number:
20240386733
In various examples, 3D object knowledge can be developed to extract diverse knowledge from large language models, and a part-grounding model can be trained to ground part semantics in terms of local shape features and spatial relations between parts. For example, knowledge that “the opening part of a mug that affords the pouring action is located on the top of the mug body and is often circular” can be grounded by identifying a previously unknown “opening” part based on its…
OBJECT SEGMENTATION USING MACHINE LEARNING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: November 21, 2024
Application Number:
20240386586
In various examples, systems and methods are disclosed relating to using neural networks for object detection or instance/semantic segmentation for, without limitation, autonomous or semi-autonomous systems and applications. In some implementations, one or more neural networks receive an image (or other sensor data representation) and a bounding shape corresponding to at least a portion of an object in the image. The bounding shape can include or be labeled with an identifier, class,…
BIDIRECTIONAL MICRORING RESONATOR-BASED PHOTONIC LINK ARCHITECTURE
Granted: November 21, 2024
Application Number:
20240385381
Optical transceiver architecture utilizing micro-ring modulators and micro-ring resonators configured to route resonant wavelengths of light injected into each micro-ring resonator's input port and through port to that micro-ring resonator's drop port and add port, respectively. The micro-ring resonators drop two distinct streams of data modulated onto the same optical wavelength, or two wavelengths separated by an integer number of free spectral ranges coupled into the micro-ring…
FERROMAGNETIC MATERIAL BASED INTEGRATED INDUCTOR IN SILICON
Granted: November 14, 2024
Application Number:
20240379731
A process for manufacturing inductors for use in integrated circuits includes embedding ferromagnetic material in a bulk silicon substrate, forming a plurality of vias in the bulk silicon substrate such that the vias bracket a volume of the bulk silicon substrate that includes the ferromagnetic material, slicing the bulk silicon substrate to form a silicon wafer, and configuring traces between top metal pads of the vias and between bottom metal pads of the vias to form a continuous path…
SYNTHETIC DATA GENERATION USING VIEWPOINT AUGMENTATION FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: October 31, 2024
Application Number:
20240362897
In various examples, systems and methods are disclosed relating to synthetic data generation using viewpoint augmentation for autonomous and semi-autonomous systems and applications. One or more circuits can identify a set of sequential images corresponding to a first viewpoint and generate a first transformed image corresponding to a second viewpoint using a first image of the set of sequential images as input to a machine-learning model. The one or more circuits can update the…
Chip Die Substrate with Edge-Mounted Capacitors
Granted: October 3, 2024
Application Number:
20240332223
An integrated circuit die substrate has one or more capacitors attached to an edge surface of the substrate. The substrate has a top surface and a bottom surface, at least one of which includes a die mounting area, and at least one of which includes system interconnect terminals. A substrate edge surface is disposed along a peripheral end of the substrate and is oriented substantially orthogonally to the top and bottom surfaces. A pair of conductive edge terminals is disposed on the…
DECIDER NETWORKS FOR REACTIVE DECISION-MAKING FOR ROBOTIC SYSTEMS AND APPLICATIONS
Granted: September 26, 2024
Application Number:
20240319713
In various examples, systems and methods are disclosed relating to decider networks for reactive decision-making, including for control of robotic systems. The decider networks can allow robotic systems to operate more collaboratively, such as by allowing the robotic systems to more frequently process and react to dynamic states of the environment and objects in the environment, such as to change decisions and/or paths of decision execution responsive to dynamic changes in logical…
