Secure execution for multiple processor devices using trusted executing environments
Granted: November 12, 2024
Patent Number:
12141268
Apparatuses, systems, and techniques to generate a trusted execution environment including multiple accelerators. In at least one embodiment, a parallel processing unit (PPU), such as a graphics processing unit (GPU), operates in a secure execution mode including a protect memory region. Furthermore, in an embodiment, a cryptographic key is utilized to protect data during transmission between the accelerators.
Integrated circuit physical security device having a security cover for an integrated circuit
Granted: November 12, 2024
Patent Number:
12142580
Devices and methods for physical chip security are disclosed. In at least one embodiment, a security module is secured to a board to restrict physical access to an integrated circuit mounted on the security module and provides one or more contacts enabling data access to the integrated circuit.
Techniques for reducing DRAM power usage in performing read and write operations
Granted: November 12, 2024
Patent Number:
12142344
Various embodiments include a memory device that is capable of performing memory access operations with reduced power consumption relative to prior approaches. The memory device receives early indication as to whether a forthcoming memory access operation is a read operation or a write operation. The memory device enables various circuits and disables other circuits depending on whether this early indication identifies an upcoming memory access operation as a read operation or a write…
Fused processing of a continuous mathematical operator
Granted: November 12, 2024
Patent Number:
12142016
Systems and methods are disclosed for fused processing of a continuous mathematical operator. Fused processing of continuous mathematical operations, such as pointwise non-linear functions without storing intermediate results to memory improves performance when the memory bus bandwidth is limited. In an embodiment, a continuous mathematical operation including at least two of convolution, upsampling, pointwise non-linear function, and downsampling is executed to process input data and…
Shape fusion for image analysis
Granted: November 12, 2024
Patent Number:
12141986
Various types of image analysis benefit from a multi-stream architecture that allows the analysis to consider shape data. A shape stream can process image data in parallel with a primary stream, where data from layers of a network in the primary stream is provided as input to a network of the shape stream. The shape data can be fused with the primary analysis data to produce more accurate output, such as to produce accurate boundary information when the shape data is used with semantic…
Adding greater realism to a computer-generated image by smoothing jagged edges
Granted: November 12, 2024
Patent Number:
12141946
During the rendering of an image, specific pixels in the image are identified where antialiasing would be helpful. Antialiasing is then performed on these identified pixels, where anti-aliasing is a technique used to add greater realism to a digital image by smoothing jagged edges. This reduces a cost of performing antialiasing by reducing a number of pixels within an image on which antialiasing is performed.
Generative neural networks with reduced aliasing
Granted: November 12, 2024
Patent Number:
12141941
Systems and methods are disclosed that improve output quality of any neural network, particularly an image generative neural network. In the real world, details of different scale tend to transform hierarchically. For example, moving a person's head causes the nose to move, which in turn moves the skin pores on the nose. Conventional generative neural networks do not synthesize images in a natural hierarchical manner: the coarse features seem to mainly control the presence of finer…
Data compression for a neural network
Granted: November 12, 2024
Patent Number:
12141689
Systems and methods for generating a representative value of a data set by first compressing a portion of values in the data set to determine a first common value and further compressing a subset of the portion of values to determine a second common value. The representative value is generated by taking the difference between the first common value and the second common value, wherein the representative value corresponds to a mathematical relationship between the first and second common…
Implementing specialized instructions for accelerating dynamic programming algorithms
Granted: November 12, 2024
Patent Number:
12141582
Various techniques for accelerating dynamic programming algorithms are provided. For example, a fused addition and comparison instruction, a three-operand comparison instruction, and a two-operand comparison instruction are used to accelerate a Needleman-Wunsch algorithm that determines an optimized global alignment of subsequences over two entire sequences. In another example, the fused addition and comparison instruction is used in an innermost loop of a Floyd-Warshall algorithm to…
Memory page access instrumentation
Granted: November 12, 2024
Patent Number:
12141451
Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The…
Virtual channel starvation-free arbitration for switches
Granted: November 5, 2024
Patent Number:
12137055
A switching system having input ports and output ports and comprising an input queued (IQ) switch with virtual channels. Typically, only one virtual channel can, at a given time, access a given output port. Typically, the IQ switch includes an arbiter apparatus that controls the input ports and output ports to ensure that an input port transmits at most one cell at a time, and/or that an output port receives a cell over only one virtual channel, and/or an output port receives at most one…
Glare mitigation using image contrast analysis for autonomous systems and applications
Granted: November 5, 2024
Patent Number:
12136249
In various examples, contrast values corresponding to pixels of one or more images generated using one or more sensors of a vehicle may be computed to detect and identify objects that trigger glare mitigating operations. Pixel luminance values are determined and used to compute a contrast value based on comparing the pixel luminance values to a reference luminance value that is based on a set of the pixels and the corresponding luminance values. A contrast threshold may be applied to the…
Implementing hardware-based memory safety for a graphic processing unit
Granted: November 5, 2024
Patent Number:
12135781
While a compiler compiles source code to create an executable binary, code is added into the compiled source code that, when executed, identifies and stores in a metadata table base and bounds information associated with memory allocations. Additionally, additional code is added into the compiled source code that enables hardware to determine a safety of memory access requests during an implementation of the compiled source code by performing an out-of-bounds (OOB) check in hardware…
Hardware-efficient PAM-3 encoder and decoder
Granted: November 5, 2024
Patent Number:
12135607
Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels and on an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on the error correction channel.
Leaf spring for an integrated circuit heat sink
Granted: October 29, 2024
Patent Number:
12129901
Various embodiments of the present disclosure relate to a leaf spring for coupling a heat sink to an integrated circuit, where the leaf spring includes a central portion that has an aperture, a first spring arm that is formed on a first side of the central portion and includes a first through-hole for a first fastener, and a second spring arm that is formed on a second side of the central portion and includes a second through-hole for a second fastener. In various embodiments, a first…
Hardware-efficient PAM-3 encoder and decoder
Granted: October 29, 2024
Patent Number:
12132590
Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels, one or more auxiliary data channels, and an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on an error correction channel.
Keeper-free volatile memory system
Granted: October 29, 2024
Patent Number:
12131775
A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
Object fence generation for lane assignment in autonomous machine applications
Granted: October 29, 2024
Patent Number:
12131556
In various examples, object fence corresponding to objects detected by an ego-vehicle may be used to determine overlap of the object fences with lanes on a driving surface. A lane mask may be generated corresponding to the lanes on the driving surface, and the object fences may be compared to the lanes of the lane mask to determine the overlap. Where an object fence is located in more than one lane, a boundary scoring approach may be used to determine a ratio of overlap of the boundary…
Hardware support for optimizing huge memory page selection
Granted: October 29, 2024
Patent Number:
12130750
Computer systems often employ virtual address translation hierarchies in which virtual memory addresses are mapped to physical memory. Use of the virtual address translation hierarchy speeds up the virtual address translation when the required mapping is stored in one of the higher levels of the hierarchy. To reduce a number of misses occurring in the virtual address translation hierarchy, huge memory pages may be selectively employed, which map larger continuous regions of virtual…
Techniques for controlling computing performance for power-constrained multi-processor computing systems
Granted: October 29, 2024
Patent Number:
12130687
A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining…
