Application of geometric acoustics for immersive virtual reality (VR)
Granted: November 7, 2023
Patent Number:
11809773
A virtual reality (VR) audio rendering system and method include spatializing microphone-captured real-world sounds according to a VR setting. In a game streaming system, when a player speaks through a microphone, the voice is processed by geometrical acoustic (GA) simulation configured for a virtual scene, and thereby spatialized audio effects specific to the scene are added. The GA simulation may include generating an impulse response using sound propagation simulation and dynamic…
Techniques for performing write training on a dynamic random-access memory
Granted: November 7, 2023
Patent Number:
11809719
Various embodiments include a memory device that is capable of performing write training operations. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device stores a first data pattern (e.g., in a FIFO memory within the memory device) or generates the first data pattern (e.g., using PRBS) that is compared with a…
Contention tracking for processor cache management
Granted: November 7, 2023
Patent Number:
11809319
The technology disclosed herein involves tracking contention and using the tracked contention to manage processor cache. The technology can be implemented in a processor's cache controlling logic and can enable the processor to track which locations in main memory are contentious. The technology can use the contentiousness of locations to determine where to store the data in cache and how to allocate and evict cache lines in the cache. In one example, the technology can store the data in…
Heterogenous voltage-based testing via on-chip voltage regulator circuits
Granted: November 7, 2023
Patent Number:
11808805
One embodiment of the present invention sets forth an integrated circuit. The integrated circuit includes a plurality of subunits associated with a plurality of operating voltages. The integrated circuit also includes one or more voltage regulator circuits that convert a first input voltage into a first plurality of output voltages during a first test, wherein the plurality of output voltages is delivered to the plurality of subunits via a plurality of output channels.
Game event recognition
Granted: November 7, 2023
Patent Number:
11806616
A game-agnostic event detector can be used to automatically identify game events. Game-specific configuration data can be used to specify types of pre-processing to be performed on media for a game session, as well as types of detectors to be used to detect events for the game. Event data for detected events can be written to an event log in a form that is both human- and process-readable. The event data can be used for various purposes, such as to generate highlight videos or provide…
Techniques for traversing data employed in ray tracing
Granted: October 31, 2023
Patent Number:
11804002
Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals.…
Fast triggering electrostatic discharge protection
Granted: October 31, 2023
Patent Number:
11804708
An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the…
Area efficient memory cell read disturb mitigation
Granted: October 31, 2023
Patent Number:
11804262
A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.
Processor and system to train machine learning models based on comparing accuracy of model parameters
Granted: October 31, 2023
Patent Number:
11804050
Apparatuses, systems, and techniques to collaboratively train one or more machine learning models. Parameter reviewers may be configured to compare sets of machine learning model parameter information in order to generate one or more machine learning models, such as neural networks.
Inverse transform sampling through ray tracing
Granted: October 31, 2023
Patent Number:
11804003
High quality image rendering can be achieved in part by using inverse transform sampling to direct sampling toward regions of greater importance, such as regions with higher brightness values, to reduce noise and improve convergence. Inverse transform sampling can be achieved more efficiently by reformulating as a ray-tracing problem, using tree traversal units that can be accelerated. A geometric mesh can be generated based on a set of cumulative distribution functions (CDFs) for…
Query-specific behavioral modification of tree traversal
Granted: October 31, 2023
Patent Number:
11804000
Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and…
Gaze detection using one or more neural networks
Granted: October 31, 2023
Patent Number:
11803759
Apparatuses, systems, and techniques are described to determine locations of objects using images including digital representations of those objects. In at least one embodiment, a gaze of one or more occupants of a vehicle is determined independently of a location of one or more sensors used to detect those occupants.
Isolating a region of a system on a chip for safety critical operations
Granted: October 31, 2023
Patent Number:
11803668
In various examples, an integrated circuit includes first and second portions operating within separate domains. The second portion has an interface that connects the first and second portions. The second portion selectively locks the interface to prevent communication with the first portion over the interface, and selectively unlocks the interface to allow communication with the first portion over the interface.
High performance synchronization mechanisms for coordinating operations on a computer system
Granted: October 31, 2023
Patent Number:
11803380
To synchronize operations of a computing system, a new type of synchronization barrier is disclosed. In one embodiment, the disclosed synchronization barrier provides for certain synchronization mechanisms such as, for example, “Arrive” and “Wait” to be split to allow for greater flexibility and efficiency in coordinating synchronization. In another embodiment, the disclosed synchronization barrier allows for hardware components such as, for example, dedicated copy or…
Visual odometry in autonomous machine applications
Granted: October 31, 2023
Patent Number:
11803192
Systems and methods for performing visual odometry more rapidly. Pairs of representations from sensor data (such as images from one or more cameras) are selected, and features common to both representations of the pair are identified. Portions of bundle adjustment matrices that correspond to the pair are updated using the common features. These updates are maintained in register memory until all portions of the matrices that correspond to the pair are updated. By selecting only common…
Using image augmentation with simulated objects for training machine learning models in autonomous driving applications
Granted: October 31, 2023
Patent Number:
11801861
In various examples, systems and methods are disclosed that preserve rich, detail-centric information from a real-world image by augmenting the real-world image with simulated objects to train a machine learning model to detect objects in an input image. The machine learning model may be trained, in deployment, to detect objects and determine bounding shapes to encapsulate detected objects. The machine learning model may further be trained to determine the type of road object…
Target-based mouse sensitivity recommendations
Granted: October 31, 2023
Patent Number:
11801443
One embodiment of a computer-implemented method for generating mouse sensitivity recommendations includes generating mouse movement data corresponding to one or more mouse movements performed by a user while interacting with a software application; generating a predicted efficiency for each mouse sensitivity level included in a plurality of mouse sensitivity levels based on the mouse movement data; and determining one or more mouse sensitivity levels to provide to the user based on the…
Method and system for customizing optimal settings using end-user preferences
Granted: October 24, 2023
Patent Number:
11798514
Embodiments of the present invention provide a novel solution that uses subjective end-user input to generate optimal image quality settings for an application. Embodiments of the present invention enable end-users to rank and/or select various adjustable application parameter settings in a manner that allows them to specify which application parameters and/or settings are most desirable to them for a given application. Based on the feedback received from end-users, embodiments of the…
Use of stashing buffers to improve the efficiency of crossbar switches
Granted: October 24, 2023
Patent Number:
11799799
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
Staggered dual-side multi-chip interconnect
Granted: October 24, 2023
Patent Number:
11798923
Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
