Techniques for ordering atomic operations
Granted: May 25, 2021
Patent Number:
11016802
In various embodiments, an ordered atomic operation enables a parallel processing subsystem to executes an atomic operation associated with a memory location in a specified order relative to other ordered atomic operations associated with the memory location. A level 2 (L2) cache slice includes an atomic processing circuit and a content-addressable memory (CAM). The CAM stores an ordered atomic operation specifying at least a memory address, an atomic operation, and an ordering number.…
Dynamically shifting video rendering tasks between a server and a client
Granted: May 18, 2021
Patent Number:
11012694
The present disclosure is directed to a method to increase virtual machine density on a server system through adaptive rendering by dynamically determining when to shift video rendering tasks between the server system and a client computing device. In another embodiment, the adaptive rendering, using various parameters, can select one or more encoding and compression algorithms to use to prepare and process the video for transmission to the client computing device. In another embodiment,…
Network adaptive latency reduction through frame rate control
Granted: May 18, 2021
Patent Number:
11012338
Novel solutions are provided for consistent Quality of Service in cloud gaming system that adaptively and dynamically compensate for poor network conditions by moderating rendered frame rates using frame rate capping to optimize for network latency savings (or surplus). In further embodiments, the encoding/sent frame rate to the client can also be managed in addition, or as an alternative to capping the rendered frame rates. The claimed embodiments not only maintain a constant Quality of…
Concurrent testing of a logic device and a memory device within a system package
Granted: May 18, 2021
Patent Number:
11011249
Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has…
Realism of scenes involving water surfaces during rendering
Granted: May 18, 2021
Patent Number:
11010963
A water surface mesh is determined for a scene to be rendered. This water surface mesh includes a grouping of geometric shapes such as triangles that represents the surface of the water. This water surface mesh is then used to create a refracted or reflected mesh. The refracted or reflected mesh shows an effect produced by the water surface's refraction or reflection of light. The relationship between the water surface mesh and the refracted or reflected mesh is then used to determine…
Deep learning based identification of difficult to test nodes
Granted: May 18, 2021
Patent Number:
11010516
Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
Systems and methods for computer simulation of detailed waves for large-scale water simulation
Granted: May 18, 2021
Patent Number:
11010509
Embodiments of the present invention provide a novel method and discretization for animating water waves. The approaches disclosed combine the flexibility of a numerical approach to wave simulation with the stability and visual detail provided by a spectrum-based approach to provide Eulerian methods for simulating large-scale oceans with highly detailed wave features. A graphics processing unit stores a one-dimensional texture referred to as a wave profile buffer that stores pre-computed…
Clock gating coupled memory retention circuit
Granted: May 11, 2021
Patent Number:
11003238
A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal…
Performance of ray-traced shadow creation within a scene
Granted: May 11, 2021
Patent Number:
11004254
A ray (e.g., a traced path of light, etc.) is generated from an originating pixel within a scene being rendered. Additionally, one or more shadow map lookups are performed for the originating pixel to estimate an intersection of the ray with alpha-tested geometry within the scene. A shadow map stores the distance of geometry as seen from the point of view of the light, and alpha-tested geometry includes objects within the scene being rendered that have a determined texture and opacity.…
Enhancing high-resolution images with data from low-resolution images
Granted: May 11, 2021
Patent Number:
11004178
Users often desire to capture certain images from an application. For example, gamers can capture displayed images from a game to show they obtained a skill level within the game or simply to capture a particular scene within the game. Existing methods of capturing images can result in low-resolution images due to limitations of the display device providing the images. This disclosure provides a method of capturing higher resolution images from source images. Techniques are also…
Network adaptive latency reduction through frame rate control
Granted: May 4, 2021
Patent Number:
10999174
Novel solutions are provided for consistent Quality of Service in cloud gaming system that adaptively and dynamically compensate for poor network conditions by moderating rendered frame rates using frame rate capping to optimize for network latency savings (or surplus). In further embodiments, the encoding/sent frame rate to the client can also be managed in addition, or as an alternative to capping the rendered frame rates. The claimed embodiments not only maintain a constant Quality of…
Reference noise compensation for single-ended signaling
Granted: May 4, 2021
Patent Number:
10999051
A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data…
Reducing video image defects by adjusting frame buffer processes
Granted: May 4, 2021
Patent Number:
10997884
The present disclosure is directed to a method to correct for visual artifacts in a virtual reality (VR) video image where there is significant motion of the video image as a result of user actions. A user may request that the video image be moved, such as a through motion detected through a VR device, i.e., turning the head, or through a request to an application, i.e., joystick feedback to a gaming application. The video image motion can cause stutter and jitter visual artifacts, when…
Sparse convolutional neural network accelerator
Granted: May 4, 2021
Patent Number:
10997496
A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. Compressed-sparse data is received for input to a processing element, wherein the compressed-sparse data encodes non-zero elements and corresponding multi-dimensional positions. The non-zero elements are processed in parallel by the processing element to produce a plurality of result values. The corresponding multi-dimensional positions are processed in parallel by…
Automated methods for conversions to a lower precision data format
Granted: May 4, 2021
Patent Number:
10997492
Aspects of the present invention are directed to computer-implemented techniques for performing data compression and conversion between data formats of varying degrees of precision, and more particularly for improving the inferencing (application) of artificial neural networks using a reduced precision (e.g., INT8) data format. Embodiments of the present invention generate candidate conversions of data output, then employ a relative measure of quality to identify the candidate conversion…
Leveraging obstacle and lane detections to determine lane assignments for objects in an environment
Granted: May 4, 2021
Patent Number:
10997435
In various examples, object fence corresponding to objects detected by an ego-vehicle may be used to determine overlap of the object fences with lanes on a driving surface. A lane mask may be generated corresponding to the lanes on the driving surface, and the object fences may be compared to the lanes of the lane mask to determine the overlap. Where an object fence is located in more than one lane, a boundary scoring approach may be used to determine a ratio of overlap of the boundary…
Real-time detection of lanes and boundaries by autonomous vehicles
Granted: May 4, 2021
Patent Number:
10997433
In various examples, sensor data representative of an image of a field of view of a vehicle sensor may be received and the sensor data may be applied to a machine learning model. The machine learning model may compute a segmentation mask representative of portions of the image corresponding to lane markings of the driving surface of the vehicle. Analysis of the segmentation mask may be performed to determine lane marking types, and lane boundaries may be generated by performing curve…
Application-specific memory scaling in multi-device systems
Granted: May 4, 2021
Patent Number:
10996865
One aspect of the current disclosure provides a method for utilizing a plurality of memories associated with a plurality of devices in a computer system. The method includes: 1) receiving a data set for executing an application employing the devices; 2) determining whether the data set is larger than a storage capacity of any of the memories; and 3) when the data set is larger than the storage capacity of any of the memories, replicating a portion of the data set across the memories and…
Power management in a multiple-processor computing device
Granted: May 4, 2021
Patent Number:
10996725
A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least…
Adaptive shading in a graphics processing pipeline
Granted: April 27, 2021
Patent Number:
10991152
One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because…
