Redriver with output receiver detection that mirrors detected termination on output to input
Granted: July 3, 2012
Patent Number:
8212587
A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to…
Clock signal noise shaping
Granted: October 25, 2011
Patent Number:
8044711
A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock…
Serial link driver interface for a communication system
Granted: March 29, 2011
Patent Number:
7915923
Method and apparatus for a communication system (100) using a driver block (200) are described. The driver block includes memory having programmable non-volatile memory cells for storing configuration settings associated with operation of the driver block (200). The driver block (200) is programmable for a selected interface protocol for operation in an adaptive equalization mode to obtain an adaptive equalization value. The adaptive equalization value is stored as a fixed equalization…
Out-of-band signaling using detector with equalizer, multiplier and comparator
Granted: October 5, 2010
Patent Number:
7808282
Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too…
Multiple channel switch using differential de-mux amplifier and differential mux equalizer
Granted: June 9, 2009
Patent Number:
7545834
A switch fabric that carries analog differential signals is constructed from 2×2 switches. Each 2×2 switch has two differential inputs that are applied to two demultiplexers. Each 2×2 switch also has two differential outputs, each driven by an equalizing mux. Each demultiplexer has two amplifiers that drive intermediate differential signals to the two equalizing muxes. Each equalizing mux has two equalizers that receive the intermediate differential signals from the two…
Swiveling offset adapter dongle for reducing blockage of closely-spaced video connectors
Granted: February 3, 2009
Patent Number:
7485007
A swivel adapter connects plugs for different video-connector standards. A smaller Display-Port (DP) connector fits into ports on a personal computer or other device, while a larger Digital Visual Interface (DVI) connector connects to a display or other device through a standard cable. When computer DP ports are tightly spaced, the wider DVI end of the swivel adapter can be twisted to make room for other DP plugs to fit into other DP ports on the computer. A swivel mechanism is located…
Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports
Granted: January 20, 2009
Patent Number:
7480303
A Pseudo-Ethernet switch has a routing table that uses Ethernet media-access controller (MAC) addresses to route Ethernet packets through a switch fabric between an input port and an output port. However, the input port and output port have Peripheral Component Interconnect Express (PCIE) interfaces that read and write PCI-Express packets to and from host-processor memories. When used in a blade system, host processor boards have PCIE physical links that connect to the PCIE ports on the…
Shared network-interface controller (NIC) using advanced switching (AS) turn-pool routing field to select from among multiple contexts for multiple processors
Granted: December 9, 2008
Patent Number:
7464174
A network connection is transparently shared among two or more processors. A shared network interface controller (NIC) has two or more sets of context registers that may include Ethernet command and pointer registers. Each set of context registers is accessed by a different processor. The processors are separated from the shared NIC by an Advanced Switching (AS) network. AS packets to write the context registers are embedded in AS packets that contain turnpool information that specifies…
Pre-emphasis and de-emphasis emulation and wave shaping using a programmable delay without using a clock
Granted: June 24, 2008
Patent Number:
7391251
An adjustable-delay filter performs wave shaping to emulate pre-emphasis or de-emphasis of transmission-line signals. The adjustable-delay filter uses analog components and does not need a clock. The receiver does not have to recover a bit-clock from the data stream, eliminating a clock recovery circuit. An input buffer receives the input signal and drives current to a summer and to an adjustable delay. The adjustable delay inverts and delays the current and drives a delayed, inverted…
Duty cycle correction using input clock and feedback clock of phase-locked-loop (PLL)
Granted: May 20, 2008
Patent Number:
7375563
A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) of the PLL drives a feedback clock that is also applied to the phase detector. An edge-triggered set-reset SR flip-flop generates a duty-cycle-corrected output clock. The SR flip-flop is set by the leading edge of the input clock, but is reset by the…
Optimized topographies for dynamic allocation of PCI express lanes using differential muxes to additional lanes to a host
Granted: April 22, 2008
Patent Number:
7363417
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. Some lanes are directly connected from the root complex host to each slot. Each slot is driven by a different port and a different direct physical layer on the host. Other lanes are configurable and can be driven by any port…
Crystal clock generator operating at third overtone of crystal's fundamental frequency
Granted: February 19, 2008
Patent Number:
7332977
A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a…
Flow-splitting and buffering PCI express switch to reduce head-of-line blocking
Granted: December 11, 2007
Patent Number:
7308523
An enhanced Peripheral Component Interconnect Express (PCIe) switch eliminates or reduces head-of-line blocking for memory reads initiated by peripheral endpoint devices. A memory-read request packet from a first peripheral endpoint device is intercepted by the enhanced PCIe switch, which generates a series of substitute request packets to the root complex and memory. The same requestor ID is used in all packets, but the original tag is replaced with a sequence of substitute tags in the…
Wide-band high-gain limiting amplifier with parallel resistor-transistor source loads
Granted: September 4, 2007
Patent Number:
7265620
An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel…
Visual or multimedia interface bus switch with level-shifted ground and input protection against non-compliant transmission-minimized differential signaling (TMDS) transmitter
Granted: August 21, 2007
Patent Number:
7259589
A bus switch chip is limited to operating with a power-supply voltage of 1.8 volts relative to a 0-volt ground. Differential bus signals switched through the bus switch chip swing from 2.7 to 3.3 volts, well above the chip's specified power-supply voltage. The bus switch chip is level-shifted by applying a 1.5-volt signal as the chip's ground, and a 3.3-volt signal as its power supply, so the chip's net power supply is within the specification at 1.8 volts. High-Definition Multimedia…
Method of making a surface mountable PCB module
Granted: July 24, 2007
Patent Number:
7246434
A printed-circuit board (PCB) module has co-planar solder pads on a bottom surface. The solder pads can be surface-mounted to pads on a main board, allowing the PCB module to be surface mounted without wire leads extending from the PCB module substrate. A cavity is formed between the solder pads on the bottom surface. The cavity is formed by milling away some of the thickness of a sacrificial insulator layer, which is the insulator layer under the solder-pad metal layer. The sacrificial…
Redundant back-up PLL oscillator phase-locked to primary oscillator with fail-over to back-up oscillator without a third oscillator
Granted: February 6, 2007
Patent Number:
7173495
A redundant-source clock generator has only two oscillators, rather than three oscillators. A secondary oscillator is phase-locked to a primary clock from a primary oscillator using a phase detector, charge pump, and filter that generate a control voltage to the secondary oscillator that determine the frequency of a secondary clock. The primary clock is compared to the secondary clock to detect primary clock failure. When clock failure is detected, a mux is switched to select a delayed…
Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host
Granted: February 6, 2007
Patent Number:
7174411
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. The host has 2N primary lanes plus one extra lane. The extra lane is allocated to a slot when another slot uses all 2N primary lanes. The extra lane ensures that a low-priority peripheral has at least one lane when a high-priority…
Converging error-recovery for multi-bit-incrementing gray code
Granted: December 12, 2006
Patent Number:
7149956
An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB.…
PLL with built-in filter-capacitor leakage-tester with current pump and comparator
Granted: November 7, 2006
Patent Number:
7132835
A filter capacitor within a phase-locked loop (PLL) can be tested using a built-in test circuit. The PLL's charge pump is deactivated while a test-current source is activated to supply a test current to the PLL filter capacitor. When the test current is larger than any leakage currents through the capacitor, the capacitor's voltage rises above a reference voltage. A test comparator compares the capacitor's voltage to the reference voltage and signals a good test result when the…
