PLX Technology Patent Applications

IN-BAND GENERATION OF LOW-FREQUENCY PERIODIC SIGNALING

Granted: May 24, 2012
Application Number: 20120128091
In a first embodiment of the present invention, a method for communicating main and auxiliary data over a transmission medium is provided, the method comprising: generating a low-frequency output pattern using a high-frequency oscillator, wherein the low-frequency output pattern contains the auxiliary data encoded in a first scheme, wherein the first scheme resembles an output pattern that would be generated by a low-frequency oscillator; sending the low-frequency output pattern through…

AUTOMATIC PORT ACCUMULATION

Granted: March 8, 2012
Application Number: 20120059957
In a first embodiment of the present invention, a method for configuring a plurality of input/output (I/O) interconnect switch ports is provided, the method comprising: starting a link training and status state machine (LTSSM) for each of the plurality of ports; placing each of the LTSSMs in a receiver detect state; changing all of the LTSSMs to a polling state only once receivers are detected or timeouts occur in the receiver detect states in each of the LTSSMs; changing all of the…

RUNTIME REPROGRAMMING OF A PROCESSOR CODE SPACE MEMORY AREA

Granted: January 19, 2012
Application Number: 20120017035
In a first embodiment of the present invention, a method for allowing a microprocessor to access a flash memory is provided, the method comprising: fetching code instructions and data from the flash memory via a unidirectional code bus coupled to a flash controller, which is coupled to a databus interface, which is coupled to the flash memory; executing the code instructions in a manner that is substantially similar to that as used for a read only memory (ROM) coupled to the…

CACHING USING VIRTUAL MEMORY

Granted: January 19, 2012
Application Number: 20120017039
In a first embodiment of the present invention, a method for caching in a processor system having virtual memory is provided, the method comprising: monitoring slow memory in the processor system to determine frequently accessed pages; for a frequently accessed page in slow memory: copy the frequently accessed page from slow memory to a location in fast memory; and update virtual address page tables to reflect the location of the frequently accessed page in fast memory.

AUTOMATED REGRESSION FAILURE MANAGEMENT SYSTEM

Granted: December 22, 2011
Application Number: 20110314334
In a first embodiment of the present invention, a method for performing regression testing on a simulated hardware is provided, the method comprising: scanning a defect database for fixed signatures; retrieving all tests in a failing instance database that correspond to the fixed signatures from the defect database; running one or more of the retrieved tests; determining if any of the retrieved tests failed during running; and for any retrieved test that failed during running, refiling…

AUTOMATIC REFERENCE FREQUENCY COMPENSATION

Granted: November 24, 2011
Application Number: 20110289338
In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device…

DYNAMIC SYSTEM CLOCK RATE

Granted: November 24, 2011
Application Number: 20110289340
In a first embodiment of the present invention, a method for dynamically adjusting a system clock of a plurality of system clock-controlled components in a system is provided, the method comprising: detecting the receipt of a command at a non-system clock-controlled component of the system; and adjusting the system clock to a fast speed based on the detecting. This embodiment may also include: determining that the command has been completed; determining that there are no outstanding…

GENERATING UNIQUE RANDOM NUMBERS FOR MULTIPLE INSTANTIATIONS

Granted: September 15, 2011
Application Number: 20110225223
In a first embodiment of the present invention, a method for generating a random number for an instance of a hardware description language definition is provided, the method comprising: generating a unique signature for the instance; applying a message digest generation process on the unique signature to arrive at a message digest having a fixed length; and applying a random number generation process on the message digest.

OPPORTUNISTIC DMA HEADER INSERTION

Granted: June 23, 2011
Application Number: 20110153875
In a first embodiment of the present invention, a method for operating an I/O interconnect midpoint device is presented, wherein the midpoint device has a direct memory access (DMA) controller and a plurality of ports, the method comprising: generating, using the DMA controller, a DMA read request; sending, using the DMA controller, the DMA read request to a first device connected to a first of the plurality of ports; receiving data responsive to the DMA read request from the first…

READ CONTROL IN A COMPUTER I/O INTERCONNECT

Granted: May 26, 2011
Application Number: 20110125947
In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first…

SUPPORTING GLOBAL INPUT/OUTPUT INTERCONNECT FEATURES ON PORTS OF A MIDPOINT DEVICE

Granted: April 28, 2011
Application Number: 20110099456
In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether…

Controlling Activation of Electronic Circuitry of Data Ports of a Communication System

Granted: March 31, 2011
Application Number: 20110074592
An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the…

DYNAMIC BUFFER POOL IN PCIEXPRESS SWITCHES

Granted: March 24, 2011
Application Number: 20110069704
In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the…

Master/Slave Transceiver Power Back-Off

Granted: March 3, 2011
Application Number: 20110051620
An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to…

DYNAMIC BUFFER POOL IN PCIEXPRESS SWITCHES

Granted: June 18, 2009
Application Number: 20090154456
In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the…

READ CONTROL IN A COMPUTER I/O INTERCONNECT

Granted: June 18, 2009
Application Number: 20090157919
In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first…