Post-distortion filter for reducing sensitivity to receiver nonlinearities
Granted: April 14, 2015
Patent Number:
9008228
Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status…
Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes
Granted: March 31, 2015
Patent Number:
8996957
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.
Equalizer for heavily clipped or compressed communications signals
Granted: March 31, 2015
Patent Number:
8995518
Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present…
Method and apparatus for translated routing in an interconnect switch
Granted: March 31, 2015
Patent Number:
8995302
A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. To enable non-transparent bridging and non-standard routing, the method may include receiving a transaction layer packet at a translated routing port of a PCIe switch, and performing translation of the address and requester ID of the packet…
Layer specific attenuation factor LDPC decoder
Granted: March 24, 2015
Patent Number:
8990661
A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein a layer specific attenuation factor is provided for each layer of the LDPC parity check matrix. An attenuation factor matrix comprising a plurality of coefficients specifies the specific attenuation factor for each layer and each iteration of the decoding process. A check node processor performs check node processing for each layer of the parity check matrix associated…
Method for estimating and correcting a carrier frequency offset over dispersive but spectrally flat channels
Granted: March 24, 2015
Patent Number:
8989316
A method for estimating a carrier frequency offset over a dispersive but spectrally flat channel comprises determining an autocorrelation of a received oversampled complex baseband digital signal, and estimating the carrier frequency offset based on an angle of the determined autocorrelation.
Method and apparatus for equalizing distortion in a digital pre-distortion observation path
Granted: March 24, 2015
Patent Number:
8989250
Methods and circuits for equalizing a linear response in an observation path of a digital pre-distorter. A method comprises generating observed signals in an observation path based on observing a transmit signal; down-converting the observed signals into intermediate frequencies using different LO frequencies; calculating a ratio using the intermediate frequencies; and equalizing the linear response of the observation path on the observed signals using the ratio. An apparatus comprises a…
Justification insertion and removal in generic mapping procedure in an optical transport network
Granted: March 24, 2015
Patent Number:
8989222
A method and apparatus are provided for generating Generic Mapping Procedure (GMP) stuff/data decisions, which avoids brute force modulo arithmetic and is efficient for hitless adjustment of ODUFIex (G.7044) in an Optical Transport Network (OTN). Addition operations are used, rather than multiplication operations, to facilitate faster and less computationally expensive calculation of data/stuff decisions, based on calculated residue values. Residue values are logically arranged in rows…
Apparatus and method for driving a transistor
Granted: March 24, 2015
Patent Number:
8988118
Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations…
System and method for avoiding error mechanisms in layered iterative decoding
Granted: March 17, 2015
Patent Number:
8984376
A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative nature of the LDPC belief propagation decoding process, such as stopping sets and trapping sets.
System and method for reduced memory storage in LDPC decoding
Granted: March 17, 2015
Patent Number:
8984365
A low-density parity check (LDPC) decoder is provided that eliminates the need to calculate customized check node codeword estimates by considering the check node processor and the variable node processor as a single processer having a shared memory for storing common variables to be used during both the check node processing and the variable node processing of the iterative decoding method.
Self-synchronous scrambler/descrambler and method for operating same
Granted: March 10, 2015
Patent Number:
8976816
A self-synchronous scrambler/descrambler and method for operating same are disclosed. A self-synchronous scrambler/descrambler comprises an M-bit Scrambler State memory for retaining M previously scrambled/descrambled bits, a SOP/EOP Zero Inserter for receiving replacing certain bytes of the bus word with a value of zero, a Mid-Packet Word Logic for scrambling/descrambling the received bits using the previously scrambled/descrambled bits from the M-bit Scrambler State memory; and a…
Systems and methods for transparently varying error correction code strength in a flash drive
Granted: March 3, 2015
Patent Number:
8972824
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.
Windowed-based decision feedback equalizer and decision feedback sequence estimator
Granted: March 3, 2015
Patent Number:
8971396
A method and system are provided for performing Decision Feedback Equalization (DFE) and Decision Feedback Sequence Estimation (DFSE) in high-throughput applications that are not latency critical. In an embodiment, overlapping blocks of samples are used to allow for the parallelization of the computation and the breaking of the critical path. In addition, the overlap of the windows addresses issues associated with performance loss due to what is termed “ramp-up” and “ramp-down”…
Multi-rate control loop for a digital phase locked loop
Granted: February 24, 2015
Patent Number:
8964925
Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP structure for the implementation of the DSP functions in the control loop for use in an ASIC and requires a reduced DSP clock rate, which in turn reduces the need for pipelining and/or high-speed libraries. Thus lower latency, better tracking performance and lower power consumption are achieved. An…
Background calibration of aperture center errors in analog to digital converters
Granted: February 10, 2015
Patent Number:
8952835
A method of background calibration of aperture center errors in a data communication system is provided. In an implementation, in response to detection of a low sampler output (“0”) in between two high sampler outputs (“1”), the method includes: determining a direction of an ADC output signal at the time of the detected low output; and adjusting timing at a selected sampler based on the determined signal direction. In an example implementation, the method includes watching for…
Method and apparatus for digital post-distortion compensation of signal non-linearities
Granted: February 3, 2015
Patent Number:
8948325
A method and apparatus to digitally remove in-band non-linear signal distortion caused by a radio frequency (RF)/intermediate frequency (IF) receiver circuit that has non-linearities, which are further affected by low-IF ADC sample aliasing.
Method and apparatus for improving the signal integrity of high-speed serial data receivers using coupled inductors
Granted: February 3, 2015
Patent Number:
8947840
Methods and apparatus improve the signal integrity of high-speed integrated circuits. Disclosed is a passive network for an input to a receiver. One embodiment of the passive network has two coupled inductors to improve both return loss and insertion loss characteristics. A shunt inductor is connected in series with the termination resistance, while a series inductor is placed in series between the pad and receiver circuitry. By exploiting deliberately-introduced mutual coupling between…
Parallel replica CDR to correct offset and gain in a baud rate sampling phase detector
Granted: January 27, 2015
Patent Number:
8942334
Apparatus and methods reduce channel-dependent phase detector offset and/or gain errors. A conventional Mueller-Muller phase detector places a main cursor at the midpoint of a pre-cursor and a post-cursor. However, for example, when the impulse response of an associated transmission line is not symmetric, the main cursor can be misaligned by conventional Mueller-Muller techniques. By providing a replica clock and data recovery path, trial and error experiments on the phase detector…
Fiber protection and power save with security
Granted: January 27, 2015
Patent Number:
8942555
A system and method for Passive Optical Networks (PON) providing integration (cross-correlation) of powersave and fiber protection, optionally with encryption, facilitating the successful operation and/or benefits that can be gained when operating a PON system with these features. A major problem with power save is the detection, since both the OLT and the ONUs rely on a valid signal in order to detect fiber failure. However, the OLT may not detect this for sleeping ONUs, and an ONU in…
