High-voltage transistor with buried conduction layer
Granted: May 13, 2003
Patent Number:
6563171
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
High-voltage lateral transistor with a multi-layered extended drain structure
Granted: April 29, 2003
Patent Number:
6555873
A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be…
Lateral power MOSFET for high switching speeds
Granted: April 29, 2003
Patent Number:
6555883
A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate structure in which the insulated gate is coupled to the gate electrode through contacts at a plurality of locations. The source electrode includes first and second segments. The first segment is interposed between the drain electrode and the gate electrode and acts as a field plate.
Integrated circuit with closely coupled high voltage output and offline transistor pair
Granted: April 22, 2003
Patent Number:
6552597
An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the…
Method and apparatus for substantially reducing electrical earth displacement current flow generated by wound components
Granted: April 15, 2003
Patent Number:
6549431
An energy transfer element having an energy transfer element input winding and an energy transfer element output winding. In one aspect, the energy transfer element input winding is capacitively coupled to the energy transfer element output winding. The energy transfer element is capacitively coupled to electrical earth. One or more additional windings are introduced as part of the energy transfer element. The one or more additional windings substantially reduce capacitive displacement…
Method and apparatus providing a multi-function terminal for a power supply controller
Granted: March 25, 2003
Patent Number:
6538908
A power supply controller having a multi-function terminal. In one embodiment, a power supply controller for switched mode power supply includes a drain terminal, a source terminal, a control terminal and a multi-function terminal. The multi-function terminal may be configured in a plurality of ways providing any one or some of a plurality of functions including on/off control, external current limit adjustments, under-voltage detection, over-voltage detection and maximum duty cycle…
Method and apparatus for reducing audio noise in a switching regulator
Granted: February 25, 2003
Patent Number:
6525514
A switching regulator utilizing on/off control that reduces audio noise at light loads by adjusting the current limit of the switching regulator. In one embodiment, a switching regulator includes a state machine that adjusts the current limit of the switching regulator based on a pattern of feedback signal values from the output of the power supply for a preceding N cycles of the drive signal. The state machine adjusts the current limit lower at light loads such that cycles are not…
Method of fabricating a high-voltage transistor
Granted: January 21, 2003
Patent Number:
6509220
A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked…
High-voltage transistor with buried conduction layer
Granted: January 7, 2003
Patent Number:
6504209
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
High-voltage transistor with buried conduction layer
Granted: December 31, 2002
Patent Number:
6501130
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
Dissipative clamping of an electrical circuit with a clamp voltage varied in response to an input voltage
Granted: December 17, 2002
Patent Number:
6496392
Dissipative clamping apparatuses and methods for electrical circuits. In one aspect of the invention, In one aspect of the invention, a method includes switching a power supply input on an energy transfer element, regulating a power supply output by switching the power supply input on the energy transfer element, clamping a voltage on the energy transfer element to a clamp voltage and varying the clamp voltage in response to the power supply input. In another aspect, an electrical…
Method of fabricating a high-voltage transistor
Granted: December 3, 2002
Patent Number:
6489190
A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of…
Switched mode power supply responsive to current derived from voltage across energy transfer element input
Granted: November 12, 2002
Patent Number:
6480399
A switched mode power supply having a regulated reflected voltage. In one embodiment, a switched mode power supply includes a power supply regulator coupled between a positive input supply rail of the power supply and a primary winding of an energy transfer element. The reflected voltage across the primary winding of the transfer element is related to the output voltage across a secondary winding of the energy transfer element according to the turns ratio of the energy transfer element.…
Method of fabricating a high-voltage transistor
Granted: October 22, 2002
Patent Number:
6468847
A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of…
High-voltage transistor with buried conduction layer
Granted: October 15, 2002
Patent Number:
6465291
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
Method and apparatus providing a multi-function terminal for a power supply controller
Granted: October 8, 2002
Patent Number:
6462971
A power supply controller having a multi-function terminal. In one embodiment, a power supply controller for switched mode power supply includes a drain terminal, a source terminal, a control terminal and a multi-function terminal. The multi-function terminal may be configured in a plurality of ways providing any one or some of a plurality of functions including on/off control, external current limit adjustments, under-voltage detection, over-voltage detection and maximum duty cycle…
Off-line converter with digital control
Granted: September 24, 2002
Patent Number:
6456475
A circuit protects a power conversion system with a feedback control loop from a fault condition. The circuit has an oscillator having an input for generating a signal with a frequency and a timer connected to the oscillator input and to the feedback control loop. The timer disables the oscillator after a period following the opening of the feedback control loop to protect the power conversion system.
Output feedback and under-voltage detection system that senses an input current representing a voltage input
Granted: August 20, 2002
Patent Number:
6438003
A switched mode controller for properly handling an under-voltage condition in a power line which includes a current mirror for receiving current from the power line; a reference current source coupled to the current mirror for supplying a reference current; and a power transistor coupled to the reference current source, the power transistor generating a pulse width modulated signal when current from the power line exceeds the reference current, the power transistor being disabled when…
High-voltage transistor with buried conduction layer
Granted: July 23, 2002
Patent Number:
6424007
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
Off-line converter with digital control
Granted: July 2, 2002
Patent Number:
6414471
A DC to DC converter comprising an energy storage element comprising an energy storage element input and an energy storage element output, the energy storage element input coupled to receive a first power level and the energy storage element output providing a second power level. The converter also comprises a feedback circuit comprising a feedback input and a feedback output, the feedback input coupled to the energy storage element output. The converter further comprises a regulator…
