Configurable, Power Supply Voltage Referenced Single-Ended Signaling with ESD Protection
Granted: March 8, 2012
Application Number:
20120057261
A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
Granted: February 23, 2012
Application Number:
20120044984
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without…
Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations
Granted: February 16, 2012
Application Number:
20120039139
Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical…
PROTOCOL FOR REFRESH BETWEEN A MEMORY CONTROLLER AND A MEMORY DEVICE
Granted: February 2, 2012
Application Number:
20120030420
The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the…
Interference cancellation in variable codelength systems for multi-access communication
Granted: February 2, 2012
Application Number:
20120027138
A receiver employs low-rate processing to synthesize the effect of high-rate interference in a received multi-rate signal. Each high-rate subchannel is analyzed on its low-rate descendents to produce symbol estimates for each low-rate symbol interval. The symbol estimates are applied to low-rate descendent subchannels, which are then combined to synthesize the effects of the high-rate interference. An interference canceller processes the synthesized interference with the received signal…
PROTOCOL INCLUDING A COMMAND-SPECIFIED TIMING REFERENCE SIGNAL
Granted: January 26, 2012
Application Number:
20120023363
Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the…
MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE
Granted: January 26, 2012
Application Number:
20120020178
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first…
Multiple Plane, Non-Volatile Memory With Synchronized Control
Granted: January 26, 2012
Application Number:
20120020161
This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the “program…
Methods and Apparatus for Determining a Phase Error in Signals
Granted: January 19, 2012
Application Number:
20120014427
An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signals. The input signals have a common phase error. The phase error determination circuit receives the sampled signals from the samplers. The phase error determination circuit generates a representation of the common phase error of the input signals in…
Synthetic Pulse Generator for Reducing Supply Noise
Granted: January 19, 2012
Application Number:
20120013361
A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of charge pulses. The number of charge pulses per unit time is proportional to the transition density of the signal, as no charge pulse is required between like symbols. The supply current used to deliver the pulses is…
MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOL
Granted: January 12, 2012
Application Number:
20120011331
The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system…
Driver Supporting Multiple Signaling Modes
Granted: December 29, 2011
Application Number:
20110316590
A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source…
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
Granted: December 22, 2011
Application Number:
20110310949
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without…
MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATION
Granted: December 15, 2011
Application Number:
20110307672
A memory system communicates at least partially temporally overlapping write-data sequences associated with independent column write accesses on data links from a memory controller to a memory device via bidirectional links. Each of these write-data sequences may be associated with a different bank set in the memory IC. These bank sets may be micro-threaded so that each bank set is independently addressable and can concurrently perform operations associated with independent commands,…
High-Speed Signaling Systems With Adaptable Pre-Emphasis and Equalization
Granted: December 15, 2011
Application Number:
20110305271
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without…
Early Read After Write Operation Memory Device, System And Method
Granted: December 8, 2011
Application Number:
20110299345
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address…
Methods for estimation and interference suppression for signal processing
Granted: December 1, 2011
Application Number:
20110292974
A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.
TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES
Granted: December 1, 2011
Application Number:
20110291693
Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse…
MEMORY INTERFACE WITH REDUCED READ-WRITE TURNAROUND DELAY
Granted: November 24, 2011
Application Number:
20110289258
Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in…
Pulse Control For NonVolatile Memory
Granted: November 24, 2011
Application Number:
20110286280
This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses…
