Adaptive Equalization Using Correlation of Edge Samples with Data Patterns
Granted: October 22, 2015
Application Number:
20150304141
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data…
Partial Response Receiver And Related Method
Granted: October 22, 2015
Application Number:
20150304136
A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects…
MULTIPLE MEMORY RANK SYSTEM AND SELECTION METHOD THEREOF
Granted: September 24, 2015
Application Number:
20150268862
A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first…
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
Granted: September 10, 2015
Application Number:
20150255144
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or…
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
Granted: August 27, 2015
Application Number:
20150243343
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or…
Memory Systems with Multiple Modules Supporting Simultaneous Access Responsive to Common Memory Commands
Granted: August 20, 2015
Application Number:
20150234754
Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write transactions. A common set of control signal lines from the controller communicates the same command and address signals to the modules. For write commands, the controller sends subsets of write data to each module over a respective subset of data lines. For read commands, each module responds with a subset of the requested data…
OPTIMIZING POWER IN A MEMORY DEVICE
Granted: June 25, 2015
Application Number:
20150179248
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at…
USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES
Granted: June 25, 2015
Application Number:
20150177815
The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a START memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts…
DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE
Granted: April 16, 2015
Application Number:
20150103605
The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense…
Clock and Data Recovery Having Shared Clock Generator
Granted: March 19, 2015
Application Number:
20150078495
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay…
RECEIVER WITH ENHANCED ISI MITIGATION
Granted: February 19, 2015
Application Number:
20150049798
A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI.
METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES
Granted: January 15, 2015
Application Number:
20150019786
A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller…
TEMPORAL REDUNDANCY
Granted: December 25, 2014
Application Number:
20140376364
A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.
TESTING THROUGH-SILICON-VIAS
Granted: December 25, 2014
Application Number:
20140376324
Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and…
MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING
Granted: November 27, 2014
Application Number:
20140351629
A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage…
DRAM METHOD, COMPONENTS, AND SYSTEM CONFIGURATIONS FOR ERROR MANAGEMENT
Granted: November 27, 2014
Application Number:
20140351673
A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and…
METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATION
Granted: November 20, 2014
Application Number:
20140341266
An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.
Low Power Memory Device
Granted: November 13, 2014
Application Number:
20140334238
A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The…
EVENT-DRIVEN CLOCK DUTY CYCLE CONTROL
Granted: November 13, 2014
Application Number:
20140333361
Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error…
TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES
Granted: November 13, 2014
Application Number:
20140333341
Methods, systems, and apparatus for testing semiconductor devices.
