Method and apparatus for coordinating memory operations among diversely-located memory components
Granted: August 4, 2005
Application Number:
20050169097
A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the present disclosure, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals…
PLL lock detection circuit using edge detection and a state machine
Granted: July 28, 2005
Application Number:
20050162199
A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the…
Periodic calibration for communication channels by drift tracking
Granted: July 28, 2005
Application Number:
20050163202
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first…
Communication channel calibration for drift conditions
Granted: July 28, 2005
Application Number:
20050163203
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…
Method and apparatus for position dependent data scheduling
Granted: July 21, 2005
Application Number:
20050160208
A method and apparatus for position dependent data scheduling for communication of data for different domains along a bus is provided. Having an awareness of the relative position of different domains along a bus, one embodiment of the present disclosure schedules bus operations to allow data from multiple bus operations to be simultaneously present on the bus while preventing interference among the data. The present disclosure is compatible with buses having a termination on one end and…
Signalling accommodation
Granted: July 14, 2005
Application Number:
20050154547
A receiving unit may implement voltage compensation using a parameters table, an analog calibration component, and/or a digital calibration component. In certain implementation(s), an integrated circuit may include a voltage driver that modifies a supplied compensated voltage based on a feedback signal. The feedback signal may be produced responsive to a distributed voltage version of the compensated voltage, to a received data signal, and to a comparison involving an expected data…
Bus line current calibration
Granted: July 7, 2005
Application Number:
20050146963
Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive…
Single-clock, strobeless signaling system
Granted: June 30, 2005
Application Number:
20050141335
A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
PYRANS AS LIQUID CRYSTALS
Granted: June 30, 2005
Application Number:
20050142300
Tetrahydropyran derivatives having at least one ester group (—CO—O—) and at least one group —CN, —NCS, —F, —Cl, —OCHF2, —OCF3, —CF3, —OCHFCF3, —OCF2CHFCF3, SF5, or —OCF2CF3; a process for preparing said tetrahydropyran derivatives, and the use of said tetrahydropyran derivatives as a component in a liquid crystal composition.
Multiple channel modules and bus systems using same
Granted: June 30, 2005
Application Number:
20050142950
Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
Periodic interface calibration for high speed communication
Granted: February 24, 2005
Application Number:
20050041683
A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines is available for data from the N line bus. The communication line on which the maintenance operation is performed, is changed after the operation is complete, so that all of the N+1 communication lines are periodically maintained, without interfering with…
Compensator for leakage through loop filter capacitors in phase-locked loops
Granted: February 17, 2005
Application Number:
20050035797
A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage…
PLL lock detection circuit using edge detection
Granted: January 20, 2005
Application Number:
20050012524
A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the…
Method and apparatus for controlling a read valid window of a synchronous memory device
Granted: January 6, 2005
Application Number:
20050005056
A method and apparatus are shown for increasing a propagation delay that may be tolerated between a memory controller and a memory device. The present invention provides for selection between two data paths for each word, where a first data path latches the data word from a DQS domain on a falling edge of a CLK0 domain and a second data patch latches the data word from the DQS domain on a rising edge of the CLK0 domain. Selection of the first data path permits larger relative propagation…
Method and apparatus for calibrating a multi-level current mode driver
Granted: January 6, 2005
Application Number:
20050005179
A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.
Memory device having programmable drive strength setting
Granted: December 2, 2004
Application Number:
20040243753
Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography…
Synchronized clocking
Granted: November 25, 2004
Application Number:
20040232956
A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. A reference clock signal is propagated along a source path and a return path, both of which pass near the registers. At each register, an averaged clock signal is generated, based on the phases of the reference clock signal on the source and return paths.…
Memory module
Granted: November 18, 2004
Application Number:
20040229480
The memory module includes a substantially rigid first circuit board having at least one memory chip disposed thereon. The memory module also includes a substantially rigid second circuit board having an array of electrical contact points disposed on a planar surface thereof. A flexible connector electrically couples the first circuit board to the second circuit board, such that the memory chip is electrically connected to the array of electrical contact points. Alternatively, The memory…
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
Granted: November 18, 2004
Application Number:
20040230743
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface…
METHOD AND APPARATUS FOR SIGNAL RECEPTION USING GROUND TERMINATION AND/OR NON-GROUND TERMINATION
Granted: November 11, 2004
Application Number:
20040222834
Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the…
