Symbol-rate phase detector for multi-PAM receiver
Granted: June 20, 2023
Patent Number:
11683206
A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB…
PAM-4 DFE architectures with symbol-transition dependent DFE tap values
Granted: June 20, 2023
Patent Number:
11683057
Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler…
Memory controller and method of data bus inversion using an error detection correction code
Granted: June 20, 2023
Patent Number:
11683050
Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read…
Method and apparatus for calibrating write timing in a memory system
Granted: June 20, 2023
Patent Number:
11682448
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or…
Interface clock management
Granted: June 20, 2023
Patent Number:
11681648
The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller…
Techniques for storing data and tags in different memory arrays
Granted: June 20, 2023
Patent Number:
11681632
A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory…
Memory controller with processor for generating interface adjustment signals
Granted: June 20, 2023
Patent Number:
11681342
A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more…
Energy-efficient error-correction-detection storage
Granted: June 13, 2023
Patent Number:
11675657
A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without…
Low-power multi-domain synchronizer
Granted: June 13, 2023
Patent Number:
11677391
A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.
Network interface with timestamping and data protection
Granted: June 13, 2023
Patent Number:
11677487
In a general aspect, a network transmission interface can include, within an egress data path, a physical coding sublayer (PCS) operating in a constant bitrate domain for transmitting data frames on a network link; a timestamp unit configured to insert timestamps in payloads of the frames; a transmission media access control (MAC) unit located at a boundary between the constant bitrate domain and a variable bitrate domain, configured to receive the frames at a variable bitrate,…
Backside security shield
Granted: June 13, 2023
Patent Number:
11677571
A physically unclonable function circuit (PUF) is used to generate a fingerprint value based on the uniqueness of the physical characteristics (e.g., resistance, capacitance, connectivity, etc.) of a tamper prevention (i.e., shielding) structure that includes through-silicon vias and metallization on the backside of the integrated circuit. The physical characteristics depend on random physical factors introduced during manufacturing. This causes the chip-to-chip variations in these…
Offset calibration for successive approximation register analog to digital converter
Granted: June 6, 2023
Patent Number:
11671108
Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are…
System and method for memory access in server communications
Granted: June 6, 2023
Patent Number:
11671522
Embodiments of the present invention are directed to memories used in server applications. More specifically, embodiments of the present invention provide a server that has memory management module that is connected to the processor using one or more DDR channels. The memory management module is configured to provide the processor local access and network access to memories on a network. There are other embodiments as well.
Live offset cancellation of the decision feedback equalization data slicers
Granted: June 6, 2023
Patent Number:
11671286
A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators…
Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link
Granted: June 6, 2023
Patent Number:
11669379
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second…
Drift tracking feedback for communication channels
Granted: June 6, 2023
Patent Number:
11669124
A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of…
Heterogenous-latency memory optimization
Granted: May 30, 2023
Patent Number:
11663138
Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are…
Methods and circuits for adaptive equalization
Granted: May 30, 2023
Patent Number:
11665028
An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.
Always-on FinFET with camouflaged punch stop implants for protecting integrated circuits from reverse engineering
Granted: May 30, 2023
Patent Number:
11664332
A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and…
Memory system component that enables clock-to-strobe skew compensation
Granted: May 30, 2023
Patent Number:
11664067
An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit…
