Data processing system having cache memory debugging support and method therefor
Granted: November 22, 2022
Patent Number:
RE49305
A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to…
Multi-stage equalizer for inter-symbol interference cancellation
Granted: November 15, 2022
Patent Number:
11502879
An equalizer includes a first feed-forward stage that provides a measure of low-frequency IS I and a second feed-forward stage that includes a cascade of stages each making an IS I estimate. The IS I estimate from each stage is further equalized by application of the measures of low-frequency IS I from the first feed-forward stage and fed to the next in the cascade of stages. The IS I estimate from the stages thus become progressively more accurate. The number of stages applied to a…
Partial response receiver
Granted: November 15, 2022
Patent Number:
11502878
A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized…
Method and system for balancing power-supply loading
Granted: November 15, 2022
Patent Number:
11502681
A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver…
Controller to detect malfunctioning address of memory device
Granted: November 15, 2022
Patent Number:
11501848
A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate…
Methods and apparatuses for addressing memory caches
Granted: November 15, 2022
Patent Number:
11500781
A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective…
Address mapping in memory systems
Granted: November 1, 2022
Patent Number:
11487676
A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.
Edge based partial response equalization
Granted: November 1, 2022
Patent Number:
11489703
An intergrated circuit (IC) chip includes receiver circuitry to receive signals from a second IC chip. The receiver circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate at least one tap weight corresponding to the at least one tap based on edge information of previously received signals.
High-bandwidth neural network
Granted: November 1, 2022
Patent Number:
11488018
One or more neural network layers are implemented by respective sets of signed multiply-accumulate units that generate dual analog result signals indicative of positive and negative product accumulations, respectively. The two analog result signals and thus the positive and negative product accumulations are differentially combined to produce a merged analog output signal that constitutes the output of a neural node within the subject neural network layer.
Semiconductor memory systems with on-die data buffering
Granted: November 1, 2022
Patent Number:
11487679
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die…
Memory component with error-detect-correct code interface
Granted: November 1, 2022
Patent Number:
11487617
A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check…
Dual-domain combinational logic circuitry
Granted: October 25, 2022
Patent Number:
11481192
A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit…
Circuits and methods for detecting and unlocking edge-phase lock
Granted: October 18, 2022
Patent Number:
11477059
A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock…
Dual loop SAR ADC with process driven architecture
Granted: October 18, 2022
Patent Number:
11476868
A dual-loop analog to digital converter (ADC) includes an asynchronous inner loop including first and second comparators and a state machine, where outputs of the first and second comparators are coupled to inputs of the state machine, and where outputs of the state machine are cross-coupled to enable ports of the first and second comparators. The ADC includes a synchronous outer loop including a successive approximation register (SAR), a digital to analog converter (DAC), and the first…
Memory module with reduced read/write turnaround overhead
Granted: October 18, 2022
Patent Number:
11474959
A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage…
Memory access during memory calibration
Granted: October 18, 2022
Patent Number:
11474957
A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also…
Dynamically changing data access bandwidth by selectively enabling and disabling data links
Granted: October 18, 2022
Patent Number:
11474590
Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link…
Memory controller for selective rank or subrank access
Granted: October 11, 2022
Patent Number:
11467986
A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect…
High-speed signaling systems and methods with adaptable, continuous-time equalization
Granted: October 11, 2022
Patent Number:
11469927
A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
DRAM interface mode with improved channel integrity and efficiency at high signaling rates
Granted: October 11, 2022
Patent Number:
11468925
An IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. For a first operating mode, the first and second read data are received after respective…
