High-bandwidth neural network
Granted: February 27, 2024
Patent Number:
11915136
One or more neural network layers are implemented by respective sets of signed multiply-accumulate units that generate dual analog result signals indicative of positive and negative product accumulations, respectively. The two analog result signals and thus the positive and negative product accumulations are differentially combined to produce a merged analog output signal that constitutes the output of a neural node within the subject neural network layer.
Memory component with input/output data rate alignment
Granted: February 27, 2024
Patent Number:
11914888
First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.
Data buffer for memory devices with unidirectional ports
Granted: February 27, 2024
Patent Number:
11914863
A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits…
Memory controller supporting nonvolatile physical memory
Granted: February 27, 2024
Patent Number:
11914508
A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
High performance, high capacity memory modules and systems
Granted: February 20, 2024
Patent Number:
11907555
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory…
Memory system design using buffer(s) on a mother board
Granted: February 20, 2024
Patent Number:
11907139
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The…
High capacity memory system with improved command-address and chip-select signaling mode
Granted: February 13, 2024
Patent Number:
11899597
A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the…
Clocking architecture supporting multiple data rates and reference edge selection
Granted: February 13, 2024
Patent Number:
11900985
A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.
Data destruction
Granted: February 13, 2024
Patent Number:
11900984
A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not…
Protocol for refresh between a memory controller and a memory device
Granted: February 13, 2024
Patent Number:
11900981
The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the…
Memory system with activate-leveling method
Granted: February 13, 2024
Patent Number:
11899571
Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations.…
Clocking architecture supporting multiple data rates and reference edge selection
Granted: February 13, 2024
Patent Number:
11900985
A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.
Data destruction
Granted: February 13, 2024
Patent Number:
11900984
A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not…
Protocol for refresh between a memory controller and a memory device
Granted: February 13, 2024
Patent Number:
11900981
The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the…
High capacity memory system with improved command-address and chip-select signaling mode
Granted: February 13, 2024
Patent Number:
11899597
A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the…
Memory system with activate-leveling method
Granted: February 13, 2024
Patent Number:
11899571
Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations.…
Stacked DRAM device and method of manufacture
Granted: February 6, 2024
Patent Number:
11894093
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory…
Dynamically changing data access bandwidth by selectively enabling and disabling data links
Granted: January 30, 2024
Patent Number:
11886272
Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link…
Interface with variable data rate
Granted: January 30, 2024
Patent Number:
11886375
A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
Memory module with programmable command buffer
Granted: January 30, 2024
Patent Number:
11886360
A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the…
