Bipolar electrode bubble detection method and apparatus
Granted: April 4, 2023
Patent Number:
11619604
A bubble detection method includes flowing a fluid through a conduit containing at least one bipolar electrode, applying an electric field across the fluid in the conduit, and detecting a presence of a bubble in the fluid when the bubble flows around or through the bipolar electrode by detecting a current or voltage output from the at least one bipolar electrode.
Non-volatile memory with variable bits per memory cell
Granted: March 28, 2023
Patent Number:
11615839
In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings…
Storage system with multiple components and method for use therewith
Granted: March 21, 2023
Patent Number:
11610642
A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses…
Hetero-plane data storage structures for non-volatile memory
Granted: March 21, 2023
Patent Number:
11610625
A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented…
Memory programming with selectively skipped verify pulses for performance improvement
Granted: March 14, 2023
Patent Number:
11605437
The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at…
Countermeasure modes to address neighbor plane disturb condition in non-volatile memory structures
Granted: March 14, 2023
Patent Number:
11605436
Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by…
Control gate signal for data retention in nonvolatile memory
Granted: March 14, 2023
Patent Number:
11605430
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is…
Efficient read of NAND with read disturb mitigation
Granted: March 7, 2023
Patent Number:
11600343
Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells…
Three-dimensional memory device containing bump stack structures and method of deformation measurement thereof
Granted: March 7, 2023
Patent Number:
11600635
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, pillar structures vertically extending through the alternating stack, bump stack structures including a base bump portion located underneath the alternating stack and a respective subset of the bump portions located in the alternating stack that overlie the base bump portion, and protrusion structures located over the alternating stack and laterally spaced from the…
Three-dimensional memory device including a composite semiconductor channel and a horizontal source contact layer and method of making the same
Granted: March 7, 2023
Patent Number:
11600634
A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor…
Deposition apparatus including an off-axis lift-and-rotation unit and methods for operating the same
Granted: March 7, 2023
Patent Number:
11598005
A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.
Three-dimensional ferroelectric memory device containing lattice-matched templates and methods of making the same
Granted: February 28, 2023
Patent Number:
11594553
A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template…
Three-dimensional memory device including molybdenum carbide or carbonitride liners and methods of forming the same
Granted: February 28, 2023
Patent Number:
11594490
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a respective conductive liner comprising…
Bonded die assembly using a face-to-back oxide bonding and methods for making the same
Granted: February 21, 2023
Patent Number:
11587943
A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second…
Bonded semiconductor die assembly containing through-stack via structures and methods for making the same
Granted: February 21, 2023
Patent Number:
11587920
A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second…
Program with consecutive verifies for non-volatile memory
Granted: February 21, 2023
Patent Number:
11587630
A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first…
Block configuration for memory device with separate sub-blocks
Granted: February 21, 2023
Patent Number:
11587619
A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set…
Prevention of latent block fails in three-dimensional NAND
Granted: February 21, 2023
Patent Number:
11587618
Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode,…
System and methods for programming nonvolatile memory having partial select gate drains
Granted: February 14, 2023
Patent Number:
11581049
Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory…
High voltage field effect transistors with self-aligned silicide contacts and methods for making the same
Granted: February 7, 2023
Patent Number:
11575015
A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.
