Apparatus and method for accelerated tiled data retrieval
Granted: April 7, 1998
Patent Number:
5736988
A method is used to access a sub-region of a two or more dimensional data region, in which said region is composed of a patchwork of individually addressable tiles. A hardware assisted mechanism is used to address, reformat, and composite data from each tile to produce a row-major subregion data stream to the consuming device. This method abstracts information about how the desired region is stored and addressed, so that further processing steps can process the data as a contiguous two…
Graphical method and system for accessing information on a communications network
Granted: April 7, 1998
Patent Number:
5737560
A system and computer-based method for permitting a computer system to access a network location using a browser application by activating a desktop icon. The system comprises a first computer readable program code means for causing the computer system to display a desktop icon associated with a file containing a network address corresponding to the network location. When the desktop icon is activated, a second computer usable program code means causes the computer to launch an instance…
Efficient ultra low drop out power regulator
Granted: April 7, 1998
Patent Number:
5736843
An ultra low drop out power regulator is described. The power regulator may be used, for example, where a dynamically fast, and electrically clean power supply at the point of use is required. The power regulator is provided as a single part with two input voltages. The higher voltage input drive the output stage so that ultra low drop out is achieved. The disclosed regulator is therefore more efficient, resulting in less heat dissipation. The regulator is packaged in a stand up package…
Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns
Granted: March 31, 1998
Patent Number:
5734877
Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master…
System and method for optimizing a source code representation as a function of resource utilization
Granted: March 31, 1998
Patent Number:
5734908
A system and method for optimizing a source code representation comprising a plurality of basic blocks are described. The optimized source code representation is to be executed in a target machine. The system operates by selecting from the source code representation a basic block pair comprising a source basic block and one or more target basic blocks. An instruction in the source basic block is identified that can be moved from the source basic block to the target basic block(s) while…
Compression connector
Granted: March 24, 1998
Patent Number:
5730605
A compression connector including a cam which securely attaches the compression connector to the backplate hook is disclosed. Specifically, in one embodiment, a backplate hook including pins located inside the receptacle is disclosed. The connector may be securely attached to the backplate hook by engaging the handle of the cam such that the cam and a second cam rotate so as to engage the pins. The movement of the cam handle compresses the connector against the surface to which the…
Method for seeding a pseudo-random number generator with a cryptographic hash of a digitization of a chaotic system
Granted: March 24, 1998
Patent Number:
5732138
A method for generating a pseudo-random numbers Initially, the state of a chaotic system is digitized to form a binary string. This binary string is then hashed to produce a second binary string. It is this second binary string which is used to seed a pseudo-random number generator. The output from the pseudo-random number generator may be used in forming a password or cryptographic key for use in a security system.
Consistently specifying way destinations through prefetching hints
Granted: March 24, 1998
Patent Number:
5732242
A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination. The portion of the hint field identifying a destination may be applied to consistently direct streamed and retained data to select portions of a cache. As a result, one type of data (e.g., retained) is lees likely to be…
System and method to reduce phase offset and phase jitter in phase-locked and delay-locked loops using self-biased circuits
Granted: March 10, 1998
Patent Number:
5727037
A system and method for using self-biased circuits to reduce phase jitter and phase offset in phase locked loops and frequency is disclosed. A self-biased apparatus for aligning a reference signal having reference phase with a feedback signal having a feedback phase includes a phase-frequency detector for comparing the reference phase and the feedback phase. The phase-frequency detector produces a phase-frequency detector output proportional to a difference between the reference phase…
Apparatus and method for page migration in a non-uniform memory access (NUMA) system
Granted: March 10, 1998
Patent Number:
5727150
A page migration controller is described. The page migration controller determines whether a memory page addressed by a memory access request should be migrated from a local processing node to a requester processing node. The page migration controller accesses an array to obtain a first count associated with the addressed memory page and the requester processing node, and a second count associated with the addressed memory page and the local processing node. The first count is…
Programmable, distributed network routing
Granted: February 24, 1998
Patent Number:
5721819
A programmable, distributed network routing system and method uses routing tables which are distributed throughout the network. Routing tables are programmed to route packets to the target device by the preferred route. When a packet is injected into the network for delivery to a particular node each router along the path taken by the packet consults its local routing table and sends the packet along the preferred route. In one implementation the router tables contained in each router…
Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a programmable register for diagnostics
Granted: February 10, 1998
Patent Number:
5717695
A method of gaining access to multiple signals internal to a semiconductor chip while minimizing the number of pins dedicated for diagnostic and testing purposes. A chip designer determines which internal signals would most likely be helpful in troubleshooting and debugging a new chip design. These signals are input to a selector. A configuration register is loaded with information specifying which ones of these signals is to be routed to the output pin(s) so that they can be monitored…
High performance sinusoidal heat sink for heat removal from electronic equipment
Granted: January 20, 1998
Patent Number:
5709263
A heat sink with undulating fins is provided. The heat sink according to this invention includes a thermally conductive base plate having a top surface and a plurality of thermally conductive fins. The fins extend upwardly from the top surface. Each fin is integral with the base plate and has an undulating surface. The fin surfaces of adjacent fins define a space for passing a cooling fluid between them.
Processor-inclusive memory module
Granted: January 20, 1998
Patent Number:
5710733
A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface…
Computer graphics system for rendering images using full spectral illumination data
Granted: January 20, 1998
Patent Number:
5710876
A computer controlled graphics system for processing an image using full spectral representations. An object in an image has an associated full spectral surface reflectance function. Each illumination source is represented by a light vector whose components represent the weights of predetermined basis functions, so that said illumination vector represents a light source in full spectral representation. A plurality of sensors each has an associated sensor response function. A user may…
Apparatus and method for integrating texture memory and interpolation logic in a computer system
Granted: January 6, 1998
Patent Number:
5706481
In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored…
DRAM for texture mapping
Granted: December 30, 1997
Patent Number:
5703810
A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative, time saving functionality during read and write operations. During a write operation, the latch can receive only those byte(s) or a row of bytes to be written. Corresponding mask bits are set to indicate those bytes to be written. Logic in the device transfers only those bytes in the row to be…
Method and an apparatus for generating reflection vectors which can be unnormalized and for using these reflection vectors to index locations on an environment map
Granted: December 30, 1997
Patent Number:
5704024
An apparatus for generating a reflection from a three-dimensional environment map. The apparatus includes a reflection vector generator which receives an eye vector and a normal vector neither of which need be normalized. This reflection vector generator generates a reflection vector without vector normalization. The reflection vector generator then couples to a decoder to supply the generated reflection vector. The decoder, in turn, determines a location where the reflection vector…
Restoration filter for truncated pixels
Granted: December 16, 1997
Patent Number:
5699079
A system and method for restoring bits of pixels prior to display where the original bits of the pixels were truncated compares each pixel to its neighbors to determine the relative value of each pixel as compared to its neighbors. First, the truncated pixel is shifted. That is, the remaining bits of the pixel are shifted to the left and additional bits are added in the least significant bit positions. Next, the pixel is compared to its neighbors to determine their relative values. For…
Software invalidation in a multiple level, multiple cache system
Granted: December 16, 1997
Patent Number:
5699551
A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target…
