Systems and methods for scalable configurations of intelligent energy storage packs
Granted: April 1, 2014
Patent Number:
8686693
A system and method for scalable configuration of intelligent energy storage packs are disclosed. According to one embodiment, a method comprises providing a first current measurement of a first energy storage cell electrically connected to a first converter circuit, and the first converter circuit controls the charge and discharge of the first energy storage cell. A first voltage measurement of the first energy storage cell is provided. First control signals are received and the first…
Semiconductor package with under bump metallization routing
Granted: March 25, 2014
Patent Number:
8680676
A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of…
Multi-turn inductors
Granted: March 18, 2014
Patent Number:
8674802
A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core…
Low profile inductors for high density circuit boards
Granted: March 18, 2014
Patent Number:
8674798
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding fauns a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height…
Conductive routings in integrated circuits using under bump metallization
Granted: March 4, 2014
Patent Number:
8664767
An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first…
Power transistor with protected channel
Granted: March 4, 2014
Patent Number:
8664728
A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an…
Vertical gate LDMOS device
Granted: February 11, 2014
Patent Number:
8647950
A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a…
Low profile inductors for high density circuit boards
Granted: January 28, 2014
Patent Number:
8638187
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height…
Sensing and feedback in a current mode control voltage regulator
Granted: January 14, 2014
Patent Number:
8629669
The disclosed embodiments of voltage regulators incorporate a current mode control architecture. In one embodiment, a comparator mechanism triggers a transition in a power switch when the error in the regulated output voltage is equal to a proportionally scaled value of current provided at an output filter. The voltage regulator includes a power switch having an input and an output. The power switch is configured to provide a first voltage during a first conduction period and a second…
Two step poly etch LDMOS gate formation
Granted: December 3, 2013
Patent Number:
8598000
A method of making a transistor is disclosed. The method starts with applying a first photoresist and performing a first etching of the first side of a gate where the gate includes an oxide layer formed over a substrate and a conductive material formed over the oxide layer. The first etching is followed by implanting an impurity region into the substrate while using the first photoresist and the conductive material as a mask making the implantation of the impurity region self-aligned to…
Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor
Granted: November 5, 2013
Patent Number:
8574973
An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS…
Voltage regulator with inductor banks
Granted: October 8, 2013
Patent Number:
8553438
A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate node. The voltage regulator…
Multiphase control systems and associated methods
Granted: October 1, 2013
Patent Number:
8547076
A control system for regulating an output voltage of a DC-DC converter having N phases, where N is an integer greater than one, includes a pulse generator and a frequency divider. The pulse generator generates a stream of fixed on-time pulses, each pulse triggered in response to current through an alternating one of the N phases falling to a threshold value. The frequency divider divides the stream of fixed on-time pulses into N phase signals for controlling the N phases. A method for…
Memory program circuit
Granted: September 3, 2013
Patent Number:
8526211
Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source…
Method of fabricating heavily doped region in double-diffused source MOSFET (LDMOS) transistor
Granted: June 4, 2013
Patent Number:
8455340
A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping…
Methods and apparatus for LDMOS transistors
Granted: April 30, 2013
Patent Number:
8431450
An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth…
Powder core material coupled inductors and associated methods
Granted: April 9, 2013
Patent Number:
8416043
A multi-phase coupled inductor includes a powder core material magnetic core and first, second, third, and fourth terminals. The coupled inductor further includes a first winding at least partially embedded in the core and a second winding at least partially embedded in the core. The first winding is electrically coupled between the first and second terminals, and the second winding electrically is coupled between the third and fourth terminals. The second winding is at least partially…
Scaling charge delivery in discontinuous mode switching regulation
Granted: March 26, 2013
Patent Number:
8405369
A voltage regulator is operated by determining whether a desired output current is below a threshold, and when the desired output current is below the threshold, generating a sequence of current pulses in a discontinuous current mode. A maximum current of the pulses is a function of the desired output current.
Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor
Granted: March 26, 2013
Patent Number:
8405148
An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS…
Start mode in switching regulation
Granted: March 19, 2013
Patent Number:
8400128
A voltage regulator is operated by, during a finite period of a voltage regular start mode having a plurality of current pulses, monotonically increasing the maximum current of the current pulses and a target voltage.
