Massive MIMO antenna and method for operating a massive MIMO antenna
Granted: October 18, 2022
Patent Number:
11476914
The present invention provides a massive MIMO antenna for wireless communication, the massive MIMO antenna comprising a plurality of antenna elements configured to receive upstream wireless signals and to transmit downstream wireless signals, the antenna elements being arranged in a matrix-like arrangement comprising rows and/or columns of antenna elements, a plurality of transceivers, each coupled to at least one of the antenna elements, and a control unit configured to selectively…
Remote active cooling heat exchanger and antenna system with the same
Granted: October 18, 2022
Patent Number:
11476556
A heat exchanger and an antenna assembly having the same are described herein that enable a compact antenna design with good thermal management. In one example, a heat exchanger is provided that includes tube-shaped body. A main cooling volume is formed between the top and bottom surfaces proximate to the outside wall. The main cooling volume has an inlet formed through the top surface and an outlet formed through the bottom surface. A return volume is formed adjacent the inside diameter…
Parallelizing simulation and hardware co-simulation of circuit designs through partitioning
Granted: October 18, 2022
Patent Number:
11475199
Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into…
Cache coherent acceleration function virtualization
Granted: October 18, 2022
Patent Number:
11474871
The embodiments herein describe a virtualization framework for cache coherent accelerators where the framework incorporates a layered approach for accelerators in their interactions between a cache coherent protocol layer and the functions performed by the accelerator. In one embodiment, the virtualization framework includes a first layer containing the different instances of accelerator functions (AFs), a second layer containing accelerator function engines (AFE) in each of the AFs, and…
Boot image file having a global partition for data processing engines of a programmable device
Granted: October 18, 2022
Patent Number:
11474826
Some examples described herein relate to a boot image file. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to compile an application to generate a boot image file. The boot image file is capable of being loaded onto and executed by a programmable device that comprises data processing engines (DPEs). The boot image file has a format comprising a platform…
Data-driven platform characteristics capture and discovery for hardware accelerators
Granted: October 18, 2022
Patent Number:
11474555
An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable…
High bandwidth CDR
Granted: October 11, 2022
Patent Number:
11469877
Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a…
Tensor compression
Granted: October 4, 2022
Patent Number:
11461625
Lossy tensor compression and decompression circuits compress and decompress tensor elements based on the values of neighboring tensor elements. The lossy compression circuit scales each decompressed tensor element of a tile by a scaling factor that is based on the maximum value that can be represented by the number of bits used to represent a compressed tensor element, and the greatest value and least value of the tensor elements of the tile. The lossy decompression circuit performs the…
Streaming FFT with bypass function
Granted: September 27, 2022
Patent Number:
11455369
Embodiments herein describe an FFT that can bypass one or more stages when processing smaller frames. For example, when all the stages in the FFT are active, the FFT can process up to a maximum supported point size. However, the particular application may only every send smaller sized frames to the FFT. Instead of unnecessarily passing these frames through the beginning stages of the FFT (which adds latency and consumes power), the embodiments herein can bypass the unneeded stages which…
Flow table modification for network accelerators
Granted: September 27, 2022
Patent Number:
11456951
Modifying a flow table for a network accelerator can include, in response to determining that a flow table of a network accelerator does not include any rules corresponding to first packet data of a first flow received from a network, forwarding the first packet data to a host computer. Subsequent to the flow table being updated to include a new rule for the first flow, for second packet data of the first flow received from the network, the second packet data can be processed using the…
Softmax calculation and architecture using a modified coordinate rotation digital computer (CORDIC) approach
Granted: September 27, 2022
Patent Number:
11455144
Apparatus and associated methods relate to providing a modified CORDIC approach and implementing the modified CORDIC approach in SoftMax calculation to reduce usage of hardware resources. In an illustrative example, a system may include (a) a first circuit configured to transform each element Vi of an input vector V into Vi=Vpi+ki·ln 2 to generate a second data set, (b) a second circuit configured to perform exponential calculations on the second data set to generate a third data set…
Compute dataflow architecture
Granted: September 20, 2022
Patent Number:
11451230
An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of…
Regular expression processor and parallel processing architecture
Granted: September 20, 2022
Patent Number:
11449344
A processing circuit includes a random access memory (RAM) configured to look up a first next state based on a first address simultaneously with looking up a second next state based on a second address. The first address is formed of a first current state and an input data and the second address is formed of a second current state and the input data. The processing circuit includes a state control circuit that receives the first and second next states, the first current state, and the…
Data processing engines with cascade connected cores
Granted: September 13, 2022
Patent Number:
11443091
An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a…
Simulation using accelerated models
Granted: September 13, 2022
Patent Number:
11443088
Simulation of a circuit design using accelerated models can include determining, using computer hardware, that a design unit of a circuit design specified in a hardware description language is a prime block and determining, using the computer hardware, an output vector corresponding to an output of the prime block. Using the computer hardware, contents of the prime block can be replaced with an accelerated simulation model specified in a high level language, wherein the accelerated…
Locking execution of cores to licensed programmable devices in a data center
Granted: September 13, 2022
Patent Number:
11443018
An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a programmable fabric of the programmable device, and an intellectual property (IP) checker circuit in the kernel logic. The IP checker circuit is configured to obtain a device identifier (ID) of the programmable device and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist,…
High speed debug hub for debugging designs in an integrated circuit
Granted: September 13, 2022
Patent Number:
11442844
An integrated circuit includes a high-speed interface configured to communicate with a host system for debugging and a debug hub coupled to the high-speed interface. The debug hub is configured to receive a debug command from the host system as memory mapped data. The integrated circuit also includes a plurality of debug cores coupled to the debug hub. Each debug core is coupled to the debug hub by channels. The debug hub is configured to translate the debug command to a data stream and…
Data mover circuitry for N-dimensional data in an integrated circuit
Granted: May 10, 2022
Patent Number:
11327677
An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC…
Three-dimensional thermal management apparatuses for electronic devices
Granted: May 10, 2022
Patent Number:
11328976
Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single…
Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip
Granted: May 10, 2022
Patent Number:
11327899
An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
