Programmed input/output mode
Granted: November 7, 2023
Patent Number:
11809367
A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured…
Wafer-scale large programmable device
Granted: October 31, 2023
Patent Number:
11803681
The embodiments herein rely on cross reticle wires (also referred to as cross die wires) to provide communication channels between programmable dies already formed on a wafer. Using cross reticle wires to facilitate x-die communication can be three to four orders of magnitude faster than using general purpose I/O. With a wafer containing cross reticle wires, various device geometries can be generated at dicing time by cutting across different reticle boundaries. This allows up to full…
Predicting a performance metric based on features of a circuit design and explaining marginal contributions of the features to the prediction
Granted: October 17, 2023
Patent Number:
11790139
A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions…
Chip bump interface compatible with different orientations and types of devices
Granted: October 10, 2023
Patent Number:
11784149
Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may…
Programmable device having hardened circuits for predetermined digital signal processing functionality
Granted: October 3, 2023
Patent Number:
11777503
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as…
Expansion card with mezzanine level connector
Granted: October 3, 2023
Patent Number:
11778743
An expansion card having a mezzanine level communication port is disclosed herein. The mezzanine level communication port frees space on the primary substrate (e.g., printed circuit board) for any one or more of a variety of expansion card components. The expansion card includes a bracket, a first communication port, a primary substrate, and a secondary substrate. The first communication port is coupled to the bracket. The primary and secondary substrates are disposed on one side of the…
Voltage sensing and biasing for wide supply range integrated circuit transceivers
Granted: October 3, 2023
Patent Number:
11777489
A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the…
Command pattern sequencer for memory calibration
Granted: October 3, 2023
Patent Number:
11775457
In one example, a command pattern sequencer includes a set of registers to store values used to configure a command sequence for configuring a memory. The command pattern sequencer further includes state machine circuitry coupled to the set of registers, the state machine circuitry configured to generate and execute the command sequence. The command pattern sequencer still further includes timing circuitry configured to manage timing between commands of the command sequence.
Compaction of multiplier and adder circuits
Granted: September 26, 2023
Patent Number:
11768663
Approaches for logic compaction include inputting an optimization directive that specifies one of area optimization or speed optimization to a synthesis tool executing on a computer processor. The synthesis tool identifies a multiplier and/or an adder specified in a circuit design and synthesizing the multiplier into logic having LUT-to-LUT connections between LUTs on separate slices of a programmable integrated circuit (IC) in response to the optimization directive specifying speed…
Heterogeneous integration module comprising thermal management apparatus
Granted: September 26, 2023
Patent Number:
11769710
Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second…
Static and automatic inference of inter-basic block burst transfers for high-level synthesis
Granted: September 19, 2023
Patent Number:
11762762
Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access…
Markov decision process based recipe generation for multi-chip apparatus
Granted: September 19, 2023
Patent Number:
11762958
Examples described herein provide for determining a recipe for identifying from which buckets integrated circuit chips are taken to form units of a multi-chip apparatus. In an example, a method uses a processor-based system and uses a Markov Decision Process. Buckets are defined based on respective characteristics of manufactured chips. Each of the manufactured chips is binned into a respective one of the buckets based on the characteristic of the respective manufactured chip. A recipe…
Offset mitigation for an analog-to-digital convertor
Granted: September 19, 2023
Patent Number:
11764797
Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first…
Integrated circuit device with edge bond dam
Granted: September 19, 2023
Patent Number:
11765836
An electronic device and methods for fabricating the same are disclosed herein that utilize a dam formed on a printed circuit board (PCB) that is positioned to substantially prevent edge bond material, utilized to secure a chip package to the PCB, from interfacing with the solder balls transmitting signals between the PCB and chip package.
Network interface device
Granted: June 27, 2023
Patent Number:
11689648
A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed…
Distributed key expansion
Granted: June 27, 2023
Patent Number:
11689361
N key generation circuits are arranged in a pipeline having N stages. Each key generation circuit is configured to generate a round key as a function of a respective input key and a respective round constant. Output signal lines that carry the round key from a key generation circuit in a stage of the pipeline, except the key generation circuit in a last stage of the pipeline, are coupled to the key generation circuit in a successive stage of the pipeline to provide the respective input…
Structure and method for a microelectronic device having high and/or low voltage supply
Granted: June 27, 2023
Patent Number:
11687108
Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input…
Wide frequency range voltage controlled oscillators
Granted: June 27, 2023
Patent Number:
11689207
Phase-locked loop circuitry generates an output signal based on transformer based voltage controlled oscillator (VCO) circuitry. The VCO circuitry includes upper band circuitry including first oscillation circuitry, a first harmonic filter circuitry coupled to the first oscillation circuitry, and a first selection transistor coupled to the first harmonic filter circuitry and a current source. The first harmonic filter circuitry filters the output signal. The lower band circuitry includes…
Core cavity noise isolation structure for use in chip packages
Granted: June 27, 2023
Patent Number:
11688675
Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing…
Control and reconfiguration of data flow graphs on heterogeneous computing platform
Granted: June 27, 2023
Patent Number:
11687327
Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can…
