Cavium Patent Grants

Memory interface with integrated tester

Granted: February 14, 2017
Patent Number: 9568542
In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a test pattern through different paths of the memory interface, and checks the result against a reference value to determine whether the components of the paths are operating within an acceptable tolerance. The memory interface can also communicate with ATE to initiate such tests and return the results to the ATE.

Distributed timer subsystem across multiple devices

Granted: February 14, 2017
Patent Number: 9568944
Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and…

Programmable ordering and prefetch

Granted: February 14, 2017
Patent Number: 9569362
An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a register storing an order configuration, which can be programmed to accommodate a given application. When suspending an access request as a result of enforcing an order configuration, the bridge may also cause a prefetch at the memory for the suspended access request. Subsequently, following the completion of a previous access request meeting the order…

System and method to provide non-coherent access to a coherent memory system

Granted: February 14, 2017
Patent Number: 9569366
In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the…

Managing skew in data signals

Granted: February 14, 2017
Patent Number: 9570128
An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by…

Systems and methods for secured backup of hardware security modules for cloud-based web services

Granted: February 14, 2017
Patent Number: 9571279
A new approach is proposed to support secured hardware security module (HSM) backup for a plurality of web services hosted in a cloud to offload their key storage, management, and crypto operations to the HSM. Each HSM is a high-performance, FIPS 140-compliant security solution for crypto acceleration of the web services. Each HSM includes multiple partitions isolated from each other, where each HSM partition is dedicated to support one of the web service hosts/servers to offload its…

Reconfigurable interconnect element with local lookup tables shared by multiple packet processing engines

Granted: February 14, 2017
Patent Number: 9571395
The invention describes the design of an interconnect element in a programmable network processor/system on-chip having multiple packet processing engines. The on-chip interconnection network for a large number of processing engines on a system can be built from an array of the proposed interconnect elements. Each interconnect element also includes local network lookup tables which allows its attached processing engines to perform lookups locally. These local lookups are much faster than…

Systems and methods for hardware accelerated timer implementation for openflow protocol

Granted: February 14, 2017
Patent Number: 9571412
A new approach is proposed to support a virtual network switch, which is a software implementation of a network switch utilizing hardware to accelerate implementation of timers of the virtual network switch under OpenFlow protocol. The approach utilizes a plurality of hardware-implemented timer blocks/rings, wherein each of the rings covers a specified time period and has a plurality of timer buckets each corresponding to an interval of expiration time of timers. When a new flow table…

Generating a non-deterministic finite automata (NFA) graph for regular expression patterns with advanced features

Granted: February 7, 2017
Patent Number: 9563399
In an embodiment, a method of compiling a pattern into a non-deterministic finite automata (NFA) graph includes examining the pattern for a plurality of elements and a plurality of node types. Each node type can correspond with an element. Each element of the pattern can be matched at least zero times. The method further includes generating a plurality of nodes of the NFA graph. Each of the plurality of nodes can be configured to match for one of the plurality of elements. The node can…

Multicast replication engine of a network ASIC and methods thereof

Granted: February 7, 2017
Patent Number: 9565136
A multicast replication engine includes a circuit implemented on a network chip to replicate packets, mirror packets and perform link switchovers. The multicast replication engine determines whether a switchover feature is enabled. If the switchover feature is not enabled, then the multicast replication engine mirrors the packet according to a mirror bit mask and to a mirror destination linked list. The mirror destination linked list corresponds to a mirroring rule. If the switchover…

Packet shaping in a network processor

Granted: January 31, 2017
Patent Number: 9559982
A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a…

Systems and methods for timing adjustment of metadata paths in a network switch under timing constraints

Granted: January 24, 2017
Patent Number: 9553819
A new approach is proposed that contemplates systems and methods to support automatic timing adjustment of a plurality of paths carrying metadata of incoming data packets in a network switch to meet their respective timing constraints. First, the paths for transmitting different pieces of metadata of incoming packets are identified in the network switch. Once the metadata paths are identified, the proposed approach identifies the timing constraints that the metadata paths need to satisfy…

Apparatus and method for fast search table update in a network switch

Granted: January 24, 2017
Patent Number: 9553829
A network switch comprises a plurality of packet processing units configured to process a received packet through multiple packet processing stages based on search result of a table. The network switch further comprises one or more memory units configured to maintain the table to be searched and provide the search result to the packet processing units. The network switch further comprises a table managing unit configured to accept a plurality of rules on bulk update to the table…

Testbench builder, system, device and method with phase synchronization

Granted: January 17, 2017
Patent Number: 9547041
A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic…

Matrix of on-chip routers interconnecting a plurality of processing engines and a method of routing using thereof

Granted: January 17, 2017
Patent Number: 9548945
Embodiments of the present invention relate to a scalable interconnection scheme of multiple processing engines on a single chip using on-chip configurable routers. The interconnection scheme supports unicast and multicast routing of data packets communicated by the processing engines. Each on-chip configurable router includes routing tables that are programmable by software, and is configured to correctly deliver incoming data packets to its output ports in a fair and deadlock-free…

Smart holding registers to enable multiple register accesses

Granted: January 10, 2017
Patent Number: 9542342
A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is…

Multi-rule approach to encoding a group of rules

Granted: January 10, 2017
Patent Number: 9544402
A multi-rule approach for encoding rules grouped in a rule chunk is provided. The approach includes a multi-rule with a multi-rule header representing headers of the rules and, in some cases, dimensional data representing dimensional data of the rules. The approach further includes disabling dimension matching of always matching dimensions, responding to an always match rule with a match response without matching, interleaving minimum/maximum values in a range field, interleaving…

Method and apparatus for memory allocation in a multi-node system

Granted: December 27, 2016
Patent Number: 9529532
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the…

Work request processor

Granted: December 27, 2016
Patent Number: 9529640
A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. pointer is added to the list based on an indication of whether…

Systems and methods for enabling access to extensible remote storage over a network as local storage via a logical storage controller

Granted: December 27, 2016
Patent Number: 9529773
A new approach is proposed that contemplates systems and methods to support elastic (extensible/flexible) storage access in real time by mapping a plurality of remote storage devices that are accessible over a network fabric as logical namespace(s) via a logical storage controller using a multitude of access mechanisms and storage network protocols. The logical storage controller exports and presents the remote storage devices to one or more VMs running on a host of the logical storage…