Cavium Patent Grants

Translation lookaside buffer invalidation suppression

Granted: June 20, 2017
Patent Number: 9684606
Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not:…

Communication and control topology for efficient testing of sets of devices

Granted: June 13, 2017
Patent Number: 9678159
A master controller includes: an interface to a CPU, an input port configured to receive a digital signal, and an output port configured to transmit a digital signal. Slave controllers each include: an interface to a device, an input port configured to receive a digital signal, and an output port configured to transmit a digital signal. A first chain bridge includes: a first set of input and output ports that couple the first chain bridge to a first chain of nodes each coupled to…

Distributing resource requests in a computing system

Granted: June 13, 2017
Patent Number: 9678717
In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.

Method and an apparatus for co-processor data plane virtualization

Granted: June 13, 2017
Patent Number: 9678779
A method and a system embodying the method for a data plane virtualization, comprising assigning each of at least one data plane a unique identifier; providing a request comprising an identifier of one of the at least one data plane together with an identifier of a virtual resource assigned to a guest; determining validity of the provided request in accordance with the identifier of the one of the at least one data plane and the identifier of the virtual resource assigned to the guest;…

Packet output processing

Granted: June 13, 2017
Patent Number: 9680742
A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the…

Method and apparatus for managing global chip power on a multicore system on chip

Granted: June 6, 2017
Patent Number: 9671844
According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power…

Voltage-controlled oscillator with improved tuning curve linearization

Granted: June 6, 2017
Patent Number: 9673753
In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the…

Method and apparatus for virtualization

Granted: May 30, 2017
Patent Number: 9665300
A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to…

Managing buffered communication between sockets

Granted: May 30, 2017
Patent Number: 9665505
A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to…

Method and an apparatus for converting interrupts into scheduled events

Granted: May 30, 2017
Patent Number: 9665508
A method and an apparatus embodying the method for converting interrupts into scheduled events, comprising receiving an interrupt at an interrupt controller; determining a vector number for the interrupt; determining properties of an interrupt work in accordance with the vector number; and scheduling the interrupt work in accordance with the properties of the interrupt work, is disclosed.

Condition code approach for comparing rule and packet data that are provided in portions

Granted: May 30, 2017
Patent Number: 9667446
A condition code approach for comparing dimension match data of a rule with corresponding data in a key is provided. The approach includes, given dimension match data divided into first and second portions, comparing the first portion with a corresponding first portion of data in a key and setting a first condition code based on the comparison. The approach further includes comparing the second portion with a corresponding second portion of key data and setting a second condition code…

Datapath subsystem, method and device utilizing memory sharing

Granted: May 16, 2017
Patent Number: 9652171
A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if…

Content search pattern matching using deterministic finite automata (DFA) graphs

Granted: May 16, 2017
Patent Number: 9652505
An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different…

Adder decoder

Granted: May 9, 2017
Patent Number: 9645790
The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n, perform a second operation of performing a bitwise left shift by 2m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1, or…

Collapsed address translation with multiple page sizes

Granted: May 9, 2017
Patent Number: 9645941
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…

Block mask register key processing by compiling data structures to traverse rules and creating a new rule set

Granted: May 9, 2017
Patent Number: 9647947
A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a routing appliance coupled to a network compiles data structures to process keys associated with a particular block mask register (BMR) of a plurality of BMRs. For each BMR of the plurality of BMRs, the processor identifies at least one of or a combination of: i) at least a portion of a field of a plurality of rules and ii) a subset of fields of the…

Merged TLB structure for multiple sequential address translations

Granted: May 2, 2017
Patent Number: 9639476
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…

Method of using bit vectors to allow expansion and collapse of header layers within packets for enabling flexible modifications and an apparatus thereof

Granted: April 25, 2017
Patent Number: 9635146
Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol…

Method of identifying internal destinations of networks packets and an apparatus thereof

Granted: April 18, 2017
Patent Number: 9628385
Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived…

Method and system for reconfigurable parallel lookups using multiple shared memories

Granted: April 11, 2017
Patent Number: 9620213
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other…