Cavium Patent Grants

Method to measure edge-rate timing penalty of digital integrated circuits

Granted: August 22, 2017
Patent Number: 9740807
Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing…

Method of dynamically renumbering ports and an apparatus thereof

Granted: August 22, 2017
Patent Number: 9742694
Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total…

Method for storing and retrieving packets in high bandwidth and low latency packet processing devices

Granted: August 15, 2017
Patent Number: 9736069
A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.

Apparatus and method for software enabled access to protected hardware resources

Granted: August 8, 2017
Patent Number: 9729320
A semiconductor includes a set of protected hardware resources, where at least one protected hardware resource stores a secure key. The semiconductor also includes a computation kernel and a memory to store a resource enablement module executed by the computation kernel. The resource enablement module selectively enables a protected hardware resource in response to a delivered key corresponding to the secure key.

Fast hardware switchover in a control path in a network ASIC

Granted: August 8, 2017
Patent Number: 9729338
A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the…

Apparatus and method for processing alternately configured longest prefix match tables

Granted: August 8, 2017
Patent Number: 9729447
A network switch includes a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries. A prefix table processor accesses in parallel, using an input network address, the alternate table representations of the individual trie and searches for a longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match from the local prefix matches is selected. The longest prefix match has an…

Lookup front end packet input processor

Granted: August 8, 2017
Patent Number: 9729527
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns…

Managing reuse information in caches

Granted: August 1, 2017
Patent Number: 9720773
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse…

Method and apparatus for aligning signals

Granted: August 1, 2017
Patent Number: 9721627
A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation,…

Method and apparatus for power control

Granted: July 11, 2017
Patent Number: 9703351
Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power.

Apparatus and method for distributed instruction trace in a processor system

Granted: July 11, 2017
Patent Number: 9703669
One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to…

Method and system for compressing data for a translation look aside buffer (TLB)

Granted: July 11, 2017
Patent Number: 9703722
An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed…

Apparatus and method for media access control scheduling with a priority calculation hardware coprocessor

Granted: July 11, 2017
Patent Number: 9706564
An apparatus includes a Media Access Control (MAC) scheduler to generate a priority value calculation request with a specified formula and a list of metrics. A hardware based priority value calculation coprocessor services the priority value calculation request in accordance with the specified formula and the list of metrics.

Filtering translation lookaside buffer invalidations

Granted: July 4, 2017
Patent Number: 9697137
A filter includes filter entries, each corresponding to a mapping between a virtual memory address and a physical memory address and including a presence indicator indicative which processing elements have the mapping present in their respective translation lookaside buffers (TLBs). A TLB invalidation (TLBI) instruction is received for a first mapping. If a first filter entry corresponding to the first mapping exists in the filter, the plurality of processing elements are partitioned…

Phase measurement and correction circuitry

Granted: July 4, 2017
Patent Number: 9698808
A circuit provides for phase adjustment of an offset clock pair, and includes an analog stage and a digital stage. The analog stage provides for generating an adjusted offset clock pair and detecting a phase difference between the adjusted offset clock pair. The digital stage operates to quantify the phase difference and provide a command for further adjusting the phase of the adjusted offset clock pair, at the analog stage, towards a target phase offset value.

Flexible instruction execution in a processor pipeline

Granted: June 27, 2017
Patent Number: 9690590
Executing instructions in a processor includes: selecting or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions, the selected one or more instructions occurring consecutively according to a program order; and executing instructions that have been issued, through multiple execution stages of a pipeline of the processor. The executing includes: determining a delay assigned to a first instruction, and sending a result of a…

Multiple ethernet ports and port types using a shared data path

Granted: June 27, 2017
Patent Number: 9692715
In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared resources may include at least one of a data path resource and a control logic resource.

Translation lookaside buffer invalidation suppression

Granted: June 20, 2017
Patent Number: 9684606
Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not:…

Distributing resource requests in a computing system

Granted: June 13, 2017
Patent Number: 9678717
In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.

Method and an apparatus for co-processor data plane virtualization

Granted: June 13, 2017
Patent Number: 9678779
A method and a system embodying the method for a data plane virtualization, comprising assigning each of at least one data plane a unique identifier; providing a request comprising an identifier of one of the at least one data plane together with an identifier of a virtual resource assigned to a guest; determining validity of the provided request in accordance with the identifier of the one of the at least one data plane and the identifier of the virtual resource assigned to the guest;…