Cavium Patent Grants

Testbench builder, system, device and method with phase synchronization

Granted: January 17, 2017
Patent Number: 9547041
A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic…

Matrix of on-chip routers interconnecting a plurality of processing engines and a method of routing using thereof

Granted: January 17, 2017
Patent Number: 9548945
Embodiments of the present invention relate to a scalable interconnection scheme of multiple processing engines on a single chip using on-chip configurable routers. The interconnection scheme supports unicast and multicast routing of data packets communicated by the processing engines. Each on-chip configurable router includes routing tables that are programmable by software, and is configured to correctly deliver incoming data packets to its output ports in a fair and deadlock-free…

Smart holding registers to enable multiple register accesses

Granted: January 10, 2017
Patent Number: 9542342
A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is…

Multi-rule approach to encoding a group of rules

Granted: January 10, 2017
Patent Number: 9544402
A multi-rule approach for encoding rules grouped in a rule chunk is provided. The approach includes a multi-rule with a multi-rule header representing headers of the rules and, in some cases, dimensional data representing dimensional data of the rules. The approach further includes disabling dimension matching of always matching dimensions, responding to an always match rule with a match response without matching, interleaving minimum/maximum values in a range field, interleaving…

Method and apparatus for memory allocation in a multi-node system

Granted: December 27, 2016
Patent Number: 9529532
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the…

Work request processor

Granted: December 27, 2016
Patent Number: 9529640
A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. pointer is added to the list based on an indication of whether…

Systems and methods for enabling access to extensible remote storage over a network as local storage via a logical storage controller

Granted: December 27, 2016
Patent Number: 9529773
A new approach is proposed that contemplates systems and methods to support elastic (extensible/flexible) storage access in real time by mapping a plurality of remote storage devices that are accessible over a network fabric as logical namespace(s) via a logical storage controller using a multitude of access mechanisms and storage network protocols. The logical storage controller exports and presents the remote storage devices to one or more VMs running on a host of the logical storage…

Multi-host processing

Granted: December 27, 2016
Patent Number: 9531647
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from multiple hosts, manages traffic among the hosts, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the…

Method and apparatus for managing processing thread migration between clusters within a processor

Granted: December 27, 2016
Patent Number: 9531690
A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an…

Phased bucket pre-fetch in a network processor

Granted: December 27, 2016
Patent Number: 9531723
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. Based on a prefetch status, a selection of the subset of rules are…

Method of using generic modification instructions to enable flexible modifications of packets and an apparatus thereof

Granted: December 27, 2016
Patent Number: 9531848
Embodiments of the apparatus for modifying packet headers relate to programmable modifications of packets by applying commands to generalized protocol headers. Each protocol header of incoming packets is represented in a generic format specific to that protocol to enable modifications to packet headers. Missing fields from a protocol header are detected, and the protocol header is expanded to a maximum size such that the protocol header contains all possible fields of that protocol,…

Method of splitting a packet into individual layers for modification and intelligently stitching layers back together after modification and an apparatus thereof

Granted: December 27, 2016
Patent Number: 9531849
Embodiments of the apparatus for modifying packet headers relate to pointer structure for splitting a packet into individual layers and for intelligently stitching them back together. The pointer structure includes N+1 layer pointers to N+1 protocol headers. The pointer structure also includes a total size of all headers. A rewrite engine uses the layer pointers to extract the first N corresponding protocol layers within the packet for modification. The rewrite engine uses the layer…

Method and apparatus for assigning resources used to manage transport operations between clusters within a processor

Granted: December 20, 2016
Patent Number: 9525630
A method, and corresponding apparatus, of assigning processing resources used to manage transport operations between a first memory cluster and one or more other memory clusters, include receiving information indicative of allocation of a subset of processing resources in each of the one or more other memory clusters to the first memory cluster, storing, in the first memory cluster, the information indicative of resources allocated to the first memory cluster, and facilitating management…

Floating mask generation for network packet flow

Granted: December 6, 2016
Patent Number: 9513926
A tag mask generation method comprises receiving a section_selector flag indicating whether a tag mask for a section of a network packet is to be generated; receiving from a parser a parse information for the network packet, wherein the parse information includes a section_pointer that indicates a location of the section in the network packet; generating a pointer based on the section_pointer when the section_selector indicates that the tag mask for the section is to be generated;…

Anchored patterns

Granted: December 6, 2016
Patent Number: 9514246
A method and apparatus relate to recognizing anchored patterns from an input stream. Patterns from a plurality of given patterns are marked as anchored patterns. An anchored state tree for the anchored patterns of the plurality of given patterns is built, including nodes representing a state of the anchored state tree. For each node of the anchored state tree, a failure value equivalent to a node representing a state in an unanchored state tree representing unanchored patterns of the…

Method of extracting data from packets and an apparatus thereof

Granted: December 6, 2016
Patent Number: 9516145
Embodiments of the apparatus for extracting data from packets relate to programmable layer commands that allow fields from packets to be extracted. A packet is split into individual layers. Each layer is given a unique layer type number that identifies the layer. Based on the layer type, each layer is expanded to a generic format. Each layer has a set of layer commands that is generic to that layer. Fields of each layer command are fieldOffset and fieldLen. These layer commands allow…

Testbench builder, system, device and method including a generic monitor and transporter

Granted: November 29, 2016
Patent Number: 9506982
A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic…

Dynamically adjusting supply voltage based on monitored chip temperature

Granted: November 29, 2016
Patent Number: 9507369
In an embodiment, a method includes monitoring a temperature of a semiconductor chip and adjusting a supply voltage to the semiconductor chip based on the monitored temperature. The temperature may be monitored by a temperature sensor located on-chip or off-chip. Adjusting the supply voltage includes increasing the supply voltage as a function of the monitored temperature decreasing. The increase to the supply voltage occurs only if the monitored temperature is below a threshold…

System and method to traverse a non-deterministic finite automata (NFA) graph generated for regular expression patterns with advanced features

Granted: November 29, 2016
Patent Number: 9507563
In one embodiment, a method of walking a non-deterministic finite automata (NFA) graph representing a pattern includes extracting a node type and an element from a node of the NFA graph. The method further includes matching a segment of a payload for the element by matching the payload for the element at least zero times, the number of times based on the node type.

Method and apparatus for handling modified constellation mapping using a soft demapper

Granted: November 29, 2016
Patent Number: 9509362
A transceiver processing hardware (“TPH”) configured to process wireless bit stream(s) includes a minimum mean square error (“MMSE”), an inverse discrete Fourier transform (“IDFT”), a demapper, a descrambler, and a combiner. While MMSE estimates transmit the bit stream, IDFT generates samples associated with the frequency of the bit stream. The demapper, in one embodiment, is configured to discard one or more unused constellation points relating to the frequency of bit stream…