Cavium Patent Grants

Method of identifying internal destinations of networks packets and an apparatus thereof

Granted: April 18, 2017
Patent Number: 9628385
Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived…

Method and system for reconfigurable parallel lookups using multiple shared memories

Granted: April 11, 2017
Patent Number: 9620213
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other…

Network processor with distributed trace buffers

Granted: April 4, 2017
Patent Number: 9612934
A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.

Control path subsystem, method and device utilizing memory sharing

Granted: April 4, 2017
Patent Number: 9612950
A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if…

Controlled dynamic de-alignment of clocks

Granted: April 4, 2017
Patent Number: 9613679
A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that drive the first and second functional units respectively. The second clock-signal generates its second clock-signal based on the first clock-signal. The clock-retardation unit dynamically causes the second clock-signal to have a target time-domain offset relative to the first clock-signal.

Work migration in a processor

Granted: April 4, 2017
Patent Number: 9614762
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. A work product may be migrated between lookup engines to complete the…

Parser engine programming tool for programmable network devices

Granted: March 28, 2017
Patent Number: 9606781
A parser engine programming tool configured to receive an input file representing a directly connected cyclical graph or tree of decision points for parsing a range of incoming packet headers, automatically generate all possible paths within the graph and thereby the associated possible headers, and convert the determined paths/headers into a proper format for programming memory of a parser engine to parse the determined headers (represented by the paths).

Packet processing system, method and device utilizing a port client chain

Granted: March 28, 2017
Patent Number: 9606942
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Managing skew in data signals with adjustable strobe

Granted: March 28, 2017
Patent Number: 9607672
An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each having inherent skew. Each data line carries a data signal. The data lines connect the memory controller to the memory. The apparatus also includes data de-skewers, each associated with a corresponding data line, a strobe interface that interfaces with a strobe line that connects the memory controller to the memory and that applies…

Controlled multi-step de-alignment of clocks

Granted: March 21, 2017
Patent Number: 9601181
An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals.

Secure software and hardware association technique

Granted: March 21, 2017
Patent Number: 9602282
Authenticated hardware and authenticated software are cryptographically associated using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. In one embodiment, critical…

Method and apparatus for optimizing finite automata processing

Granted: March 21, 2017
Patent Number: 9602532
A method, and corresponding apparatus and system are provided for optimizing matching at least one regular expression pattern in an input stream by walking at least one finite automaton in a speculative manner. The speculative manner may include iteratively walking at least two nodes of a given finite automaton, of the at least one finite automaton, in parallel, with a segment, at a current offset within a payload, of a packet in the input stream, based on positively matching the segment…

Compiler with mask nodes

Granted: March 14, 2017
Patent Number: 9595003
A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. The plurality of nodes may be stride nodes, mask nodes, or a combination…

Messaging with flexible transmit ordering

Granted: March 14, 2017
Patent Number: 9596193
In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an…

Method and apparatus encoding a rule for a lookup request in a processor

Granted: March 14, 2017
Patent Number: 9596222
In one embodiment, a method includes encoding a key matching rule having at least one dimension by storing in a memory (i) a header of the key matching rule that has at least one header field, and (ii) at least one rule value field of the key matching rule corresponding to one of the dimensions.

Edge rate control calibration

Granted: March 7, 2017
Patent Number: 9590797
In an example embodiment, a circuit includes an oscillator providing a set of clock phase signals. A main edge rate controller (ERC) coupled to the oscillator is configured to adjust an edge rate of each clock phase signal of the set of clock phase signals. An interpolator coupled to the main ERC is configured to interpolate the adjusted set of clock phase signals to provide at least one desired phase output signal. An edge rate controller calibrator comprises a ring oscillator including…

Packet processing system, method and device utilizing memory sharing

Granted: February 28, 2017
Patent Number: 9582215
A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if…

Algorithm to achieve optimal layout of decision logic elements for programmable network devices

Granted: February 28, 2017
Patent Number: 9582251
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate…

Barrel compactor system, method and device having cell combination logic

Granted: February 28, 2017
Patent Number: 9584635
A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.

Memory interface with integrated tester

Granted: February 14, 2017
Patent Number: 9568542
In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a test pattern through different paths of the memory interface, and checks the result against a reference value to determine whether the components of the paths are operating within an acceptable tolerance. The memory interface can also communicate with ATE to initiate such tests and return the results to the ATE.