DIGITAL CONTROL METHOD FOR IMPROVING HEAVY-TO-LIGHT (STEP DOWN) LOAD TRANSIENT RESPONSE OF SWITCH MODE POWER SUPPLIES
Granted: August 25, 2011
Application Number:
20110204862
A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor.
GLUE-LOGIC BASED METHOD AND SYSTEM FOR MINIMIZING LOSSES IN OVERSAMPLED DIGITALLY CONTROLLED DC-DC CONVERTERS
Granted: August 25, 2011
Application Number:
20110204988
A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor.
EXTENDABLE N-CHANNEL DIGITAL PULSE-WIDTH/PULSE-FREQUENCY MODULATOR
Granted: August 18, 2011
Application Number:
20110199164
A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency…
METHODOLOGY FOR STORING AND UPDATING ON-CHIP REVISION LEVEL
Granted: July 28, 2011
Application Number:
20110185337
Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.
MEANS TO DETECT A MISSING PULSE AND REDUCE THE ASSOCIATED PLL PHASE BUMP
Granted: June 24, 2010
Application Number:
20100156482
A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock…
SELF-TUNING SENSORLESS DIGITAL CURRENT-MODE CONTROLLER WITH ACCURATE CURRENT SHARING FOR MULTIPHASE DC-DC CONVERTERS
Granted: June 10, 2010
Application Number:
20100141230
Embodiments of the present invention concern a multiphase switch-mode power supply. The multiple phase switch-mode power supply can have at least one switch and a digital controller to control the switching of the at least one switch. During a calibration period, the digital controller can freeze the current of all of the multiple phases except for a phase being calibrated. This can be done by fixing the current reference of the phases except for the phase being calibrated.
UNIVERSAL AND FAULT-TOLERANT MULTIPHASE DIGITAL PWM CONTROLLER FOR HIGH-FREQUENCY DC-DC CONVERTERS
Granted: June 10, 2010
Application Number:
20100141349
A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.
OPEN-DRAIN OUTPUT BUFFER FOR SINGLE-VOLTAGE-SUPPLY CMOS
Granted: May 27, 2010
Application Number:
20100127762
An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching…
MULTI-CHANNEL DIGITAL PULSE WIDTH MODULATOR (DPWM)
Granted: May 13, 2010
Application Number:
20100117752
A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple…
ESR ZERO ESTIMATION AND AUTO-COMPENSATION IN DIGITALLY CONTROLLED BUCK CONVERTERS
Granted: May 13, 2010
Application Number:
20100117615
One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the…
GRAY CODE CURRENT MODE ANALOG-TO-DIGITAL CONVERTER
Granted: March 18, 2010
Application Number:
20100066579
One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital…
LOW POWER METHOD OF RESPONSIVELY INITIATING FAST RESPONSE TO A DETECTED CHANGE OF CONDITION
Granted: November 12, 2009
Application Number:
20090278522
A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state without boost.
INTERRUPT BASED MULTIPLEXED CURRENT LIMIT CIRCUIT
Granted: November 5, 2009
Application Number:
20090273498
A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC…
SELF-TUNING DIGITAL CURRENT ESTIMATOR FOR LOW-POWER SWITCHING CONVERTERS
Granted: October 29, 2009
Application Number:
20090267582
A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator.
LOW-VOLTAGE CMOS SPACE-EFFICIENT 15 KV ESD PROTECTION FOR COMMON-MODE HIGH-VOLTAGE RECEIVERS
Granted: October 22, 2009
Application Number:
20090262474
An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each…
COMBINATION OFFSET VOLTAGE AND BIAS CURRENT AUTO-ZERO CIRCUIT
Granted: September 17, 2009
Application Number:
20090231029
A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier.
AUTO-DETECTING CMOS INPUT CIRCUIT FOR SINGLE-VOLTAGE-SUPPLY CMOS
Granted: July 16, 2009
Application Number:
20090180227
An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and…
METHODS OF USING PREDICTIVE ANALOG TO DIGITAL CONVERTERS
Granted: December 4, 2008
Application Number:
20080297381
Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a…
Means To Detect A Missing Pulse And Reduce The Associated PLL Phase Bump
Granted: November 6, 2008
Application Number:
20080272808
A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock…
Means To Reduce The PLL Phase Bump Caused By A Missing Clock Pulse
Granted: November 6, 2008
Application Number:
20080273648
A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period.…
