INCREMENTAL PRECISION NETWORKS USING RESIDUAL INFERENCE AND FINE-GRAIN QUANTIZATION
Granted: May 16, 2024
Application Number:
20240160931
One embodiment provides for a computer-readable medium storing instructions that cause one or more processors to perform operations comprising determining a per-layer scale factor to apply to tensor data associated with layers of a neural network model and converting the tensor data to converted tensor data. The tensor data may be converted from a floating point datatype to a second datatype that is an 8-bit datatype. The instructions further cause the one or more processors to generate…
RADIO FREQUENCY FRONT-END STRUCTURES
Granted: May 16, 2024
Application Number:
20240164010
Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES
Granted: May 16, 2024
Application Number:
20240162289
Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the…
PACKAGE SUBSTRATE WITH ALTERNATING DIELECTRIC MATERIAL LAYER PAIRS
Granted: May 16, 2024
Application Number:
20240162191
Embodiments of a package substrate includes: a conductive via in a first layer, the first layer comprising a positive-type photo-imageable dielectric; a conductive trace in a second layer, the second layer comprising a negative-type photo-imageable dielectric; and an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers. The conductive via is…
PACKAGE ARCHITECTURE WITH MICROFLUIDIC CHANNELS IN GLASS SUBSTRATES
Granted: May 16, 2024
Application Number:
20240162158
Embodiments of a microelectronic assembly includes: an interposer comprising a first portion in contact along an interface with a second portion; a first integrated circuit (IC) die embedded in a dielectric material in the first portion of the interposer; and a second IC die coupled to the first portion of the interposer opposite to the second portion, wherein: the second portion comprises a glass substrate with a channel within the glass substrate, a portion of the channel has an…
BUMPLESS HYBRID ORGANIC GLASS INTERPOSER
Granted: May 16, 2024
Application Number:
20240162157
A bumpless hybrid organic glass interposer. One or more high density pattern (HDP) routing layers are placed on a functional, thin, carrier, separate from the intended organic substrate patch or package. The HDP layer(s) is/are then attached to the substrate package. The interposers achieve electrical connections between the HDP layer and underlying routing layer of the substrate package by utilizing a self-align dry etch process through landing pads connected to the HDP routing.
TOOLS AND METHODS FOR SUBTRACTIVE METAL PATTERNING
Granted: May 16, 2024
Application Number:
20240162058
Disclosed herein are tools and methods for subtractively patterning metals. These tools and methods may permit the subtractive patterning of metal (e.g., copper, platinum, etc.) at pitches lower than those achievable by conventional etch tools and/or with aspect ratios greater than those achievable by conventional etch tools. The tools and methods disclosed herein may be cost-effective and appropriate for high-volume manufacturing, in contrast to conventional etch tools.
METHOD AND SYSTEM OF IMAGE PROCESSING WITH MULTI-SKELETON TRACKING
Granted: May 16, 2024
Application Number:
20240161316
A method and system of image processing with multi-skeleton tracking uses a temporal object key point loss metric.
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
Granted: May 16, 2024
Application Number:
20240161227
Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.
MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT
Granted: May 16, 2024
Application Number:
20240161226
Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein…
VARIABLE PRECISION AND MIX TYPE REPRESENTATION OF MULTIPLE LAYERS IN A NETWORK
Granted: May 16, 2024
Application Number:
20240160910
In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.
APPROXIMATING ACTIVATION FUNCTION IN NEURAL NETWORK WITH LOOK-UP TABLE HAVING HYBRID ARCHITECTURE
Granted: May 16, 2024
Application Number:
20240160695
A non-linear activation function may be approximated by linear functions. The input range of the activation function may be divided into input segments. One or more input segments may be selected based on statistical analysis of input data elements in the input range. A parameter of a first linear function that approximates the activation function for at least part of a selected input segment may be stored in a first portion of a first look-up table (LUT). The first portion of the first…
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
Granted: May 16, 2024
Application Number:
20240160585
A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to…
CACHE OPTIMIZATION MECHANISM
Granted: May 16, 2024
Application Number:
20240160581
An apparatus includes a central processing unit (CPU), including a plurality of processing cores, each having a cache memory, a fabric interconnect coupled to the plurality of processing cores and cryptographic circuitry, coupled to the fabric interconnect including mesh stop station to receive memory data and determine a destination of the memory data and encryption circuitry to encrypt/decrypt the memory data based on a destination of the memory data.
DYNAMIC MICROSERVICES ALLOCATION MECHANISM
Granted: May 16, 2024
Application Number:
20240160488
A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of micro service s cluster.
INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS ENVIRONMENT
Granted: May 16, 2024
Application Number:
20240160478
An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control…
INTEGER SQUARE 1ULP HARDWARE MULTIPLIER
Granted: May 16, 2024
Application Number:
20240160407
Described herein is a truncated modified Booth squarer that is commutative and accurate to 1 unit in the last place. In various embodiments, the truncated Booth squarer is a radix-4 Booth squarer or a radix-8 Booth squarer. The truncated Booth squarer can be included within integer, floating-point, or fixed-point units within a graphics processor or compute accelerator, including matrix accelerator units or tensor processors.
COMPUTATION OF CORRECTLY ROUNDED FLOATING POINT SUMMATION
Granted: May 16, 2024
Application Number:
20240160405
Computer computation of correctly rounded floating point summation is described. An example of apparatus includes a first circuit to sort multiple floating point (FP) values based on an exponent of each FP value and store the sorted FP values in a buffer, and to provide the plurality of FP values for summation sequentially in a sorted order starting with a FP value having a smallest exponent; a second circuit to iteratively sum the FP values and store an accumulated value, generate and…
STREAMLINED DEVELOPMENT AND DEPLOYMENT OF AUTOENCODERS
Granted: May 9, 2024
Application Number:
20240152756
In one embodiment, a method of training an autoencoder neural network includes determining autoencoder design parameters for the autoencoder neural network, including an input image size for an input image, a compression ratio for compression of the input image into a latent vector, and a latent vector size for the latent vector. The input image size is determined based on a resolution of training images and a size of target features to be detected. The compression ratio is determined…
METHOD AND SYSTEM OF AUTOMATIC CONTENT-DEPENDENT IMAGE PROCESSING ALGORITHM SELECTION
Granted: May 9, 2024
Application Number:
20240153033
A method, system, and article is directed to automatic content-dependent image processing algorithm selection.
