Methods and apparatus for distributed training of a neural network
Granted: April 23, 2024
Patent Number:
11966843
Methods, apparatus, systems and articles of manufacture for distributed training of a neural network are disclosed. An example apparatus includes a neural network trainer to select a plurality of training data items from a training data set based on a toggle rate of each item in the training data set. A neural network parameter memory is to store neural network training parameters. A neural network processor is to generate training data results from distributed training over multiple…
Monitoring downlink control channels for unlicensed operation
Granted: April 23, 2024
Patent Number:
11968689
Methods, systems, and storage media are described for monitoring downlink control information (DCI). In particular, some embodiments may be directed to monitoring DCI for an indication of channel occupancy time (COT) information. Other embodiments may be described and/or claimed.
Apparatus and method for 5G quality of service indicator management
Granted: April 23, 2024
Patent Number:
11968559
A device to host a service producer in a 5G system (or 5G system architecture), a method to be performed at the device, and a non-transitory storage device storing instructions to be executed at the device. The method includes: decoding a request from a service consumer to manage one or more 5G quality of service (QoS) indicators (5QIs), each 5QI including a 5QI value and corresponding 5QI characteristics; configuring one or more network functions (NFs) of the 5GS with the 5QIs based on…
Encoding and decoding video
Granted: April 23, 2024
Patent Number:
11968380
An apparatus for encoding and decoding video receives a request to decode a current video frame. The apparatus determines whether encoding is within a threshold for a previous video frame. Additionally, the apparatus waits for the encoding to start if the encoding is within the threshold. Further, the apparatus provides a signal to begin encoding the current video frame. Also, the apparatus submits a decode workload to a graphics processor unit (GPU) for the current video frame. The…
Injection-locked clock-multiplication for mixer local oscillator (LO) generation
Granted: April 23, 2024
Patent Number:
11967980
Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed…
Dual threshold voltage (VT) channel devices and their methods of fabrication
Granted: April 23, 2024
Patent Number:
11967615
Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a…
Microelectronic assemblies with communication networks
Granted: April 23, 2024
Patent Number:
11967580
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least…
Multi-camera device
Granted: April 23, 2024
Patent Number:
11967129
Apparatuses, methods and storage medium associated with multi-camera devices are disclosed herein. In embodiments, a multi-camera device may include 3 or more camera sensors disposed on a world facing side of the multi-camera device. Further, the multi-camera device may be configured to provide a soft shutter button at a location on an opposite side to the world facing side, coordinated with locations of the 3 or more camera sensors that reduces likelihood of blocking of one or more of…
Ordering of shader code execution
Granted: April 23, 2024
Patent Number:
11966998
Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU). In some examples, the GPU is configured to execute a shader program that is to identify at least two code blocks that are independent from each other and cause execution of an unexecuted independent code block with available data based on use of a scoreboard to track data availability for independent code blocks. In some examples, execution of the shader…
Systems and methods implementing an intelligent machine learning tuning system providing multiple tuned hyperparameter solutions
Granted: April 23, 2024
Patent Number:
11966860
Disclosed examples include after a first tuning of hyperparameters in a hyperparameter space, selecting first hyperparameter values for respective ones of the hyperparameters; generating a polygonal shaped failure region in the hyperparameter space based on the first hyperparameter values; setting the first hyperparameter values to failure before a second tuning of the hyperparameters; and selecting second hyperparameter values for the respective ones of the hyperparameters in a second…
Busbar
Granted: April 23, 2024
Patent Number:
D1023975
Apparatuses, methods, and systems for instructions to request a history reset of a processor core
Granted: April 23, 2024
Patent Number:
11966742
Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the…
Topology-driven structured trunk routing
Granted: April 23, 2024
Patent Number:
11966681
The computer executable instructions include a command that accepts multiple user input through various command options. The command encapsulates and implements multiple original software algorithms that convert trunking design intent, expressed via the command options, into trunks on multiple layers of a process technology node. Once executed, the command generates shapes of trunks of specified topology on specified layers. The command includes a set of options to generate a simple or…
Glitch attack mitigation for in-vehicle networks
Granted: April 23, 2024
Patent Number:
11966503
Systems, apparatuses, and methods to mitigate effects of glitch attacks on a broadcast communication bus are provided. The voltage levels of the communication bus are repeatedly sampled to identify glitch attacks. The voltage level on the communication bus can be overdriven or overwritten to either corrupt received messages or correct received messages.
Methods and apparatus to detect side-channel attacks
Granted: April 23, 2024
Patent Number:
11966473
Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. Example instructions cause one or more processors to generate an event vector based on one or more counts corresponding to tasks performed by a central processing unit; determine distances between the event vector and weight vectors of neurons in a self-organizing map; select a neuron of the neurons that results based on a determined distance; identify neurons that neighbor the…
Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits
Granted: April 23, 2024
Patent Number:
11966334
Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space…
Link affinitization to reduce transfer latency
Granted: April 23, 2024
Patent Number:
11966330
Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an…
Read retry to selectively disable on-die ECC
Granted: April 23, 2024
Patent Number:
11966286
A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.
Systems and methods for isolating an accelerated function unit and/or an accelerated function context
Granted: April 23, 2024
Patent Number:
11966281
Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining…
Apparatus and methods for thermal management of electronic user devices based on user activity
Granted: April 23, 2024
Patent Number:
11966268
Apparatus and methods for thermal management of electronic user devices are disclosed herein. An example apparatus includes at least one of a user presence detection analyzer to identify a presence of a user relative to an electronic device based on first sensor data generated by a first sensor or at least one of an image data analyzer or a motion data analyzer to determine a gesture of the user relative to the device based on second sensor data generated by a second sensor; a thermal…
