Adaptive Pixel Sampling Order for Temporally Dense Rendering
Granted: August 24, 2023
Application Number:
20230269391
A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
CMOS SIGNALING FRONT END FOR EXTRA SHORT REACH LINKS
Granted: August 24, 2023
Application Number:
20230269119
A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
KEEPER-FREE VOLATILE MEMORY SYSTEM
Granted: August 24, 2023
Application Number:
20230267992
A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
TRANSCEIVER SYSTEM WITH END-TO-END RELIABILITY AND ORDERING PROTOCOLS
Granted: August 17, 2023
Application Number:
20230261794
Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a…
Simultaneous Bi-directional Hybrid Transceiver for Single-Ended Voltage Mode Signaling
Granted: August 3, 2023
Application Number:
20230246661
A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
Denoising ATAC-Seq Data With Deep Learning
Granted: August 3, 2023
Application Number:
20230245718
The present invention provides methods, systems, computer program products that use deep learning with neural networks to denoise ATAC-seq datasets. The methods, systems, and programs provide for increased efficiency, accuracy, and speed in identifying genomic sites of chromatin accessibility in a wide range of tissue and cell types.
Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
Granted: July 27, 2023
Application Number:
20230237313
A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
Staggered Dual-Side Multi-Chip Interconnect
Granted: June 22, 2023
Application Number:
20230197696
Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
SLEW SIGNAL SHAPER CIRCUIT
Granted: June 22, 2023
Application Number:
20230197127
To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.
CAMERA BLOCKAGE DETECTION FOR AUTONOMOUS DRIVING SYSTEMS
Granted: June 15, 2023
Application Number:
20230186639
Systems and methods for detecting blockages in images are described. An example method may include receiving a plurality of images captured by a camera installed on an apparatus. The method may include identifying one or more candidate blocked regions in the plurality of images. Each of the candidate blocked regions may contain image data caused by blockages in the camera's field-of-view. The method may further include assigning scores to the one or more candidate blocked regions based…
SYSTEMS AND METHODS FOR DETECTION OF CRYPTOCURRENCY MINING USING PROCESSOR METADATA
Granted: May 4, 2023
Application Number:
20230133110
A system and method may determine if a class of process (e.g. NN execution, cryptocurrency mining, graphic processing) is executing on a processor, or which class is executing, by calculating or determining features from execution telemetry or measurements collected from processors executing processes, and determining from at least a subset of the features the likelihood that the processor is executing the class of process. Execution telemetry may include data regarding or describing the…
SYSTEMS AND METHODS FOR DETECTION OF CRYPTOCURRENCY MINING USING PROCESSOR METADATA
Granted: May 4, 2023
Application Number:
20230133110
A system and method may determine if a class of process (e.g. NN execution, cryptocurrency mining, graphic processing) is executing on a processor, or which class is executing, by calculating or determining features from execution telemetry or measurements collected from processors executing processes, and determining from at least a subset of the features the likelihood that the processor is executing the class of process. Execution telemetry may include data regarding or describing the…
SOFTWARE-DIRECTED DIVERGENT BRANCH TARGET PRIORITIZATION
Granted: April 13, 2023
Application Number:
20230115044
Instruction set architecture extensions to configure priority ordering of divergent target branch instructions on SIMT computing platforms to enable tools such as compilers (e.g., under influence of execution profilers) or human software developers to configure branch direction prioritization explicitly in code. Extensions for simple (two-way) branch instructions as well as multi-target (more than two branch target instructions) are disclosed.
ADVERSARIAL SCENARIOS FOR SAFETY TESTING OF AUTONOMOUS VEHICLES
Granted: March 16, 2023
Application Number:
20230079196
Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.
CURRENT FLATTENING CIRCUIT FOR PROTECTION AGAINST POWER SIDE CHANNEL ATTACKS
Granted: February 23, 2023
Application Number:
20230053487
Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
MEMORY INTERFACE WITH REDUCED ENERGY TRANSMIT MODE
Granted: February 9, 2023
Application Number:
20230043152
PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.
CONVERGENCE AMONG CONCURRENTLY EXECUTING THREADS
Granted: February 9, 2023
Application Number:
20230038061
Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.
MEMORY INTERFACE WITH REDUCED ENERGY TRANSMIT MODE
Granted: February 9, 2023
Application Number:
20230043152
PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.
CONVERGENCE AMONG CONCURRENTLY EXECUTING THREADS
Granted: February 9, 2023
Application Number:
20230038061
Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.
AREA EFFICIENT MEMORY CELL READ DISTURB MITIGATION
Granted: December 22, 2022
Application Number:
20220406371
A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.
